文件名称:ddr_verilog
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DDR控制器的VERILOG代码；状态机；读写；刷新等操作-ddr controller,verilog
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下载文件列表
ddr_verilog_xilinx\.recordref
..................\AutoConstraint_top.sdc
..................\compxlib.cfg
..................\ddr_verilog_xilinx.ise
..................\ddr_verilog_xilinx.restore
..................\define.v
..................\.oc\ddr_xilinx.pdf
..................\glbl.v
..................\model.list
..................\modelsim.ini
..................\mt46v4m16.v
..................\readme.txt
..................\rpt_top.areasrr
..................\rpt_top_areasrr.htm
..................\run_options.txt
..................\string_decode_fn.v
..................\synplicity.ucf
..................\...tmp\top.plg
..................\......\top_flink.htm
..................\......\top_srr.htm
..................\......\top_toc.htm
..................\tb_top.v
..................\test.fdo
..................\test.udo
..................\test_wave.fdo
..................\top.edn
..................\top.fse
..................\top.htm
..................\top.map
..................\top.ncf
..................\top.prj
..................\top.sap
..................\top.sdc
..................\top.srd
..................\top.srm
..................\top.srr
..................\top.srs
..................\top.szr
..................\top.tlg
..................\top.ucf
..................\top_compile.tcl
..................\top_func.v
..................\top_map.tcl
..................\top_summary.html
..................\transcript
..................\traplog.tlg
..................\verif\top.vif
..................\vsim.wlf
..................\wave.do
..................\.ork\addr_latch\_primary.dat
..................\....\..........\_primary.vhd
..................\....\brst_cntr\_primary.dat
..................\....\.........\_primary.vhd
..................\....\clk_dlls\_primary.dat
..................\....\........\_primary.vhd
..................\....\.ontroller\_primary.dat
..................\....\..........\_primary.vhd
..................\....\.slt_cntr\_primary.dat
..................\....\.........\_primary.vhd
..................\....\data_dly\_primary.dat
..................\....\........\_primary.vhd
..................\....\.....path\_primary.dat
..................\....\.........\_primary.vhd
..................\....\.dr_ctlr\_primary.dat
..................\....\........\_primary.vhd
..................\....\....dq_io_16\_primary.dat
..................\....\............\_primary.vhd
..................\....\....iob_ff\_primary.dat
..................\....\..........\_primary.vhd
..................\....\glbl\_primary.dat
..................\....\....\_primary.vhd
..................\....\mt46v4m16\_primary.dat
..................\....\.........\_primary.vhd
..................\....\rcd_cntr\_primary.dat
..................\....\........\_primary.vhd
..................\....\test\_primary.dat
..................\....\....\_primary.vhd
..................\....\.op\_primary.dat
..................\....\...\_primary.vhd
..................\....\user_int\_primary.dat
..................\....\........\_primary.vhd
..................\....\_info
..................\....\.opt\D__Xilinx_10.1_ISE_verilog_mti_se_secureip__info
..................\....\....\D__Xilinx_10.1_ISE_verilog_mti_se_unimacro_ver__info
..................\....\....\D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@b@u@f@g_fast.dt2
..................\....\....\D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@c@l@k@d@l@l_fast.asm
..................\....\....\D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@c@l@k@d@l@l_fast.dt2
..................\....\....\D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@f@d@d@r@r@s@e_fast.asm
..................\....\....\D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@f@d@d@r@r@s@e_fast.dt2
..................\....\....\D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@f@d_fast.asm
..................\....\....\D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@f@d_fast.dt2
..................\....\....\D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@i@b@u@f@g_fast.dt2
..................\....\....\D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@i@b@u@f_fast.dt2
..................\....\....\D__Xili