文件名称:NANDFlash-controller-BCH-code
介绍说明－－下载内容均来自于网络，请自行研究使用
提出一种应用于 NAND Flash 控制器的并行 BCH 编/译码器，在译码阶段引入流水线操作和分组预取译码操作，提升 BCH 码的译
码效率。实验结果表明，在 NAND Flash 的 2 KB 页读取操作中，该编/译码器纠正 8 bit 的随机错误只需要 565 个周期的译码时间，是采用按页预取译码方式所需时间的 1/4。
-Anew architecture of parallel BCH encoder and decoder applied in NAND Flash Controller is proposed. In order to obviously increase the throughput of decoder, pipeline operation and prefetch decoding in group operation are applied in the design. It takes 565 cycles to correct 8 bit random error after NAND Flash’s 2 KB page read operation, which is a quarter of the time cost by prefetch & decode in page.
码效率。实验结果表明，在 NAND Flash 的 2 KB 页读取操作中，该编/译码器纠正 8 bit 的随机错误只需要 565 个周期的译码时间，是采用按页预取译码方式所需时间的 1/4。
-Anew architecture of parallel BCH encoder and decoder applied in NAND Flash Controller is proposed. In order to obviously increase the throughput of decoder, pipeline operation and prefetch decoding in group operation are applied in the design. It takes 565 cycles to correct 8 bit random error after NAND Flash’s 2 KB page read operation, which is a quarter of the time cost by prefetch & decode in page.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
NANDFlash控制器的BCH编_译码器设计.kdh