文件名称:juanji2

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 262kb
  • 下载次数:
  • 1次
  • 提 供 者:
  • 杨**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

本程序是在Xilinx ISE上编写的,它完成(2,1,6)卷积码的译码工作。里面有源程序和用以仿真的测试文件-The program is written on Xilinx ISE, it completed (2,1,6) convolutional code decoding. Source and for the simulation of the test file inside
(系统自动生成,下载前可以参看下载内容)

下载文件列表





juanji2\juanji_yi\.cxl.mti_se.version

.......\.........\.lso

.......\.........\compxlib.cfg

.......\.........\compxlib.log

.......\.........\iseconfig\juanjiy.xreport

.......\.........\.........\juanji_yi.projectmgr

.......\.........\.........\test_juanjiy.xreport

.......\.........\juanjiy.cmd_log

.......\.........\juanjiy.lso

.......\.........\juanjiy.ngc

.......\.........\juanjiy.ngr

.......\.........\juanjiy.prj

.......\.........\juanjiy.stx

.......\.........\juanjiy.syr

.......\.........\juanjiy.v

.......\.........\juanjiy.xst

.......\.........\juanjiy_envsettings.html

.......\.........\juanjiy_summary.html

.......\.........\juanjiy_xst.xrpt

.......\.........\juanji_yi.gise

.......\.........\juanji_yi.xise

.......\.........\modelsim.ini

.......\.........\test_juanjiy.cmd_log

.......\.........\test_juanjiy.fdo

.......\.........\test_juanjiy.lso

.......\.........\test_juanjiy.prj

.......\.........\test_juanjiy.stx

.......\.........\test_juanjiy.syr

.......\.........\test_juanjiy.udo

.......\.........\test_juanjiy.v

.......\.........\test_juanjiy.xst

.......\.........\test_juanjiy_envsettings.html

.......\.........\test_juanjiy_summary.html

.......\.........\test_juanjiy_wave.fdo

.......\.........\test_juanjiy_xst.xrpt

.......\.........\transcript

.......\.........\vsim.wlf

.......\.........\webtalk_pn.xml

.......\.........\.ork\@_opt\vopt1d83r7

.......\.........\....\.....\vopt1yi5q4

.......\.........\....\.....\vopt24gm8r

.......\.........\....\.....\vopt6k5i8r

.......\.........\....\.....\vopt94vf8r

.......\.........\....\.....\vopt9f9s53

.......\.........\....\.....\voptbcgnr4

.......\.........\....\.....\voptdzyn53

.......\.........\....\.....\voptfw5jr4

.......\.........\....\.....\voptgfkj53

.......\.........\....\.....\vopticvgr4

.......\.........\....\.....\voptkrwgi7

.......\.........\....\.....\voptnwgcr4

.......\.........\....\.....\voptq8ici7

.......\.........\....\.....\voptqjfz8r

.......\.........\....\.....\vopttwa983

.......\.........\....\.....\voptv35w8r

.......\.........\....\.....\voptvgnc43

.......\.........\....\.....\voptxc0683

.......\.........\....\.....\voptz0c843

.......\.........\....\.....\voptzjtr8r

.......\.........\....\.....\_deps

.......\.........\....\glbl\_primary.dat

.......\.........\....\....\_primary.dbs

.......\.........\....\....\_primary.vhd

.......\.........\....\juanjiy\_primary.dat

.......\.........\....\.......\_primary.dbs

.......\.........\....\.......\_primary.vhd

.......\.........\....\test_juanjiy\_primary.dat

.......\.........\....\............\_primary.dbs

.......\.........\....\............\_primary.vhd

.......\.........\....\_info

.......\.........\....\_vmake

.......\.........\xst\work\hdllib.ref

.......\.........\...\....\vlg41\test__juanjiy.bin

.......\.........\...\....\...5A\juanjiy.bin

.......\.........\_xmsgs\pn_parser.xmsgs

.......\.........\......\xst.xmsgs

.......\sim.do

.......\vsim.wlf

.......\work\@f@f\verilog.asm

.......\....\....\verilog.rw

.......\....\....\_primary.dat

.......\....\....\_primary.dbs

.......\....\....\_primary.vhd

.......\....\.g@f@a@d@d\verilog.asm

.......\....\..........\verilog.rw

.......\....\..........\_primary.dat

.......\....\..........\_primary.dbs

.......\....\..........\_primary.vhd

.......\....\juanjiy\verilog.asm

.......\....\.......\verilog.rw

.......\....\.......\_primary.dat

.......\....\.......\_primary.dbs

.......\....\.......\_primary.vhd

.......\....\lcpmult\verilog.asm

.......\....\.......\verilog.rw

.......\....\.......\_primary.dat

.......\....\.......\_primary.dbs

.......\....\.......\_primary.vhd

.......\....\test_juanjiy\verilog.asm

.......\....\............\verilog.rw

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