文件名称:number_clock
介绍说明－－下载内容均来自于网络，请自行研究使用
典型实例 用FPGA来开发一个 数字跑表，实现跑表的全部功能-FPGA Verilg clock
(系统自动生成,下载前可以参看下载内容)
下载文件列表
典型实例3_2 数字跑表
.....................\实战训练3 数字跑表
.....................\...................\cmp_state.ini
.....................\...................\DOC
.....................\...................\...\说明.txt
.....................\...................\paobiao.asm.rpt
.....................\...................\paobiao.cdf
.....................\...................\paobiao.done
.....................\...................\paobiao.fit.eqn
.....................\...................\paobiao.fit.rpt
.....................\...................\paobiao.fit.summary
.....................\...................\paobiao.flow.rpt
.....................\...................\paobiao.map.eqn
.....................\...................\paobiao.map.rpt
.....................\...................\paobiao.map.summary
.....................\...................\paobiao.pin
.....................\...................\paobiao.pof
.....................\...................\paobiao.qpf
.....................\...................\paobiao.qsf
.....................\...................\paobiao.qws
.....................\...................\paobiao.saf
.....................\...................\paobiao.sim.rpt
.....................\...................\paobiao.sof
.....................\...................\paobiao.tan.rpt
.....................\...................\paobiao.tan.summary
.....................\...................\paobiao.vwf
.....................\...................\SRC
.....................\...................\...\paobiao.v