文件名称:risc_cpu-OK
介绍说明－－下载内容均来自于网络，请自行研究使用
夏宇闻 verilog数字系统设计教程源码 第二版，实现了简单的RISC CPU。印刷版有误，已改正。- A simple RISC CPU Verilog HDL source code. Work well.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
risc_cpu OK\accum.v
...........\addr_decode.v
...........\adr.v
...........\alu.v
...........\clk_gen.v
...........\counter.v
...........\cpu.v
...........\cputop.v
...........\datactl.v
...........\machine.v
...........\machinectl.v
...........\ram.v
...........\register.v
...........\rom.v
...........\test1.dat
...........\test1.pro
...........\test2.dat
...........\test2.pro
...........\test3.dat
...........\test3.pro
risc_cpu OK
...........\addr_decode.v
...........\adr.v
...........\alu.v
...........\clk_gen.v
...........\counter.v
...........\cpu.v
...........\cputop.v
...........\datactl.v
...........\machine.v
...........\machinectl.v
...........\ram.v
...........\register.v
...........\rom.v
...........\test1.dat
...........\test1.pro
...........\test2.dat
...........\test2.pro
...........\test3.dat
...........\test3.pro
risc_cpu OK