文件名称:DDDRR_SDRAM_cD
介绍说明－－下载内容均来自于网络，请自行研究使用
DDR SRAM控制器的verilog完整设设计文档（包含有完整的verilog源代码），
-DDR SRAM controller the verilog complete set design document (contains the complete source code verilog)
-DDR SRAM controller the verilog complete set design document (contains the complete source code verilog)
(系统自动生成,下载前可以参看下载内容)
下载文件列表
DDDRR_SDRAM_cD\DDR SDRAM\DDR SDRAM\DDR SDRAM\mem_interface_top.txt
..............\.........\.........\.........\mem_interface_top_addr_gen_0.txt
..............\.........\.........\.........\mem_interface_top_backend_fifos_0.txt
..............\.........\.........\.........\mem_interface_top_backend_rom_0.txt
..............\.........\.........\.........\mem_interface_top_cmp_rd_data_0.txt
..............\.........\.........\.........\mem_interface_top_controller_iobs_0.txt
..............\.........\.........\.........\mem_interface_top_data_gen_16.txt
..............\.........\.........\.........\mem_interface_top_data_path_0.txt
..............\.........\.........\.........\mem_interface_top_data_path_iobs_0.txt
..............\.........\.........\.........\mem_interface_top_data_tap_inc.txt
..............\.........\.........\.........\mem_interface_top_data_write_0.txt
..............\.........\.........\.........\mem_interface_top_ddr_controller_0.txt
..............\.........\.........\.........\mem_interface_top_idelay_ctrl.txt
..............\.........\.........\.........\mem_interface_top_infrastructure.txt
..............\.........\.........\.........\mem_interface_top_infrastructure_iobs_0.txt
..............\.........\.........\.........\mem_interface_top_iobs_0.txt
..............\.........\.........\.........\mem_interface_top_main_0.txt
..............\.........\.........\.........\mem_interface_top_parameters_0.txt
..............\.........\.........\.........\mem_interface_top_pattern_compare8.txt
..............\.........\.........\.........\mem_interface_top_RAM_D_0.txt
..............\.........\.........\.........\mem_interface_top_rd_data_0.txt
..............\.........\.........\.........\mem_interface_top_rd_data_fifo_0.txt
..............\.........\.........\.........\mem_interface_top_rd_wr_addr_fifo_0.txt
..............\.........\.........\.........\mem_interface_top_tap_ctrl_0.txt
..............\.........\.........\.........\mem_interface_top_tap_logic_0.txt
..............\.........\.........\.........\mem_interface_top_test_bench_0.txt
..............\.........\.........\.........\mem_interface_top_top_0.txt
..............\.........\.........\.........\mem_interface_top_user_interface_0.txt
..............\.........\.........\.........\mem_interface_top_v4_dm_iob.txt
..............\.........\.........\.........\mem_interface_top_v4_dqs_iob.txt
..............\.........\.........\.........\mem_interface_top_v4_dq_iob.txt
..............\.........\.........\.........\mem_interface_top_wr_data_fifo_16.txt
..............\.........\.........\.........\使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器.pdf
..............\.........\使用说明请参看右侧注释====〉〉.txt
..............\.........\DDR SDRAM\DDR SDRAM
..............\.........\DDR SDRAM
..............\DDR SDRAM
DDDRR_SDRAM_cD
..............\.........\.........\.........\mem_interface_top_addr_gen_0.txt
..............\.........\.........\.........\mem_interface_top_backend_fifos_0.txt
..............\.........\.........\.........\mem_interface_top_backend_rom_0.txt
..............\.........\.........\.........\mem_interface_top_cmp_rd_data_0.txt
..............\.........\.........\.........\mem_interface_top_controller_iobs_0.txt
..............\.........\.........\.........\mem_interface_top_data_gen_16.txt
..............\.........\.........\.........\mem_interface_top_data_path_0.txt
..............\.........\.........\.........\mem_interface_top_data_path_iobs_0.txt
..............\.........\.........\.........\mem_interface_top_data_tap_inc.txt
..............\.........\.........\.........\mem_interface_top_data_write_0.txt
..............\.........\.........\.........\mem_interface_top_ddr_controller_0.txt
..............\.........\.........\.........\mem_interface_top_idelay_ctrl.txt
..............\.........\.........\.........\mem_interface_top_infrastructure.txt
..............\.........\.........\.........\mem_interface_top_infrastructure_iobs_0.txt
..............\.........\.........\.........\mem_interface_top_iobs_0.txt
..............\.........\.........\.........\mem_interface_top_main_0.txt
..............\.........\.........\.........\mem_interface_top_parameters_0.txt
..............\.........\.........\.........\mem_interface_top_pattern_compare8.txt
..............\.........\.........\.........\mem_interface_top_RAM_D_0.txt
..............\.........\.........\.........\mem_interface_top_rd_data_0.txt
..............\.........\.........\.........\mem_interface_top_rd_data_fifo_0.txt
..............\.........\.........\.........\mem_interface_top_rd_wr_addr_fifo_0.txt
..............\.........\.........\.........\mem_interface_top_tap_ctrl_0.txt
..............\.........\.........\.........\mem_interface_top_tap_logic_0.txt
..............\.........\.........\.........\mem_interface_top_test_bench_0.txt
..............\.........\.........\.........\mem_interface_top_top_0.txt
..............\.........\.........\.........\mem_interface_top_user_interface_0.txt
..............\.........\.........\.........\mem_interface_top_v4_dm_iob.txt
..............\.........\.........\.........\mem_interface_top_v4_dqs_iob.txt
..............\.........\.........\.........\mem_interface_top_v4_dq_iob.txt
..............\.........\.........\.........\mem_interface_top_wr_data_fifo_16.txt
..............\.........\.........\.........\使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器.pdf
..............\.........\使用说明请参看右侧注释====〉〉.txt
..............\.........\DDR SDRAM\DDR SDRAM
..............\.........\DDR SDRAM
..............\DDR SDRAM
DDDRR_SDRAM_cD