文件名称:video_add_program
介绍说明－－下载内容均来自于网络，请自行研究使用
用FPGA实现的视频叠加系统，电子设计大赛的，程序-FPGA implementation of video overlay system, Electronic Design Contest, the program
(系统自动生成,下载前可以参看下载内容)
下载文件列表
video_add_program
.................\.lso
.................\LINE_BUFFER.tfi
.................\PALtoRGB.v
.................\Untitled.mcs
.................\Untitled.prm
.................\Untitled.sig
.................\_ngo
.................\....\netlist.lst
.................\_xmsgs
.................\......\bitgen.xmsgs
.................\......\map.xmsgs
.................\......\ngdbuild.xmsgs
.................\......\par.xmsgs
.................\......\trce.xmsgs
.................\......\xst.xmsgs
.................\dcm_dsgn.v
.................\dcm_dsgn.xaw
.................\dcm_dsgn_arwz.ucf
.................\de_interlacing.prj
.................\de_interlacing.stx
.................\de_interlacing.v
.................\de_interlacing.xst
.................\deint_v2mult_4L.prj
.................\deint_v2mult_4L.stx
.................\deint_v2mult_4L.tfi
.................\deint_v2mult_4L.v
.................\deint_v2mult_4L.xst
.................\device_usage_statistics.html
.................\i2c.v
.................\i2c_control.vhd
.................\i2c_data_gen.v
.................\i2c_summary.html
.................\lf_decode.v
.................\line_buffer.v
.................\neg_edge_detect.v
.................\pipe_line_delay.v
.................\rst_generator.v
.................\shift24.v
.................\shift8.vhd
.................\shift8_v.v
.................\slaver.v
.................\smartpreview.twr
.................\special_svga_timing_generation.v
.................\spi_slave.v
.................\spi_stabilizer.v
.................\spi_stablizer.tfi
.................\sram0.v
.................\sram1.v
.................\sram_addr_gen.v
.................\svga_defines.v
.................\switch_control.v
.................\system.ucf
.................\test_VGA.bld
.................\test_VGA.cmd_log
.................\test_VGA.ise
.................\test_VGA.lso
.................\test_VGA.ncd
.................\test_VGA.ngc
.................\test_VGA.ngd
.................\test_VGA.ngr
.................\test_VGA.ntrc_log
.................\test_VGA.pad
.................\test_VGA.par
.................\test_VGA.pcf
.................\test_VGA.prj
.................\test_VGA.ptwx
.................\test_VGA.restore
.................\test_VGA.stx
.................\test_VGA.syr
.................\test_VGA.twr
.................\test_VGA.twx
.................\test_VGA.unroutes
.................\test_VGA.ut
.................\test_VGA.v
.................\test_VGA.xpi
.................\test_VGA.xst
.................\test_VGA_guide.ncd
.................\test_VGA_map.map
.................\test_VGA_map.mrp
.................\test_VGA_map.ncd
.................\test_VGA_map.ngm
.................\test_VGA_map.xrpt
.................\test_VGA_ngdbuild.xrpt
.................\test_VGA_pad.csv
.................\test_VGA_pad.txt
.................\test_VGA_par.xrpt
.................\test_VGA_prev_built.ngd
.................\test_VGA_summary.html
.................\test_VGA_summary.xml
.................\test_VGA_usage.xml
.................\test_VGA_vhdl.prj
.................\test_VGA_xdb
.................\............\cst.xbcd
.................\............\tmp
.................\............\...\ise
.................\............\...\...\__OBJSTORE__
.................\............\...\...\............\Autonym
.................\............\...\...\............\HierarchicalDesign
.................\............\...\...\............\..................\HDProject