文件名称:ledflow
- 所属分类：
- 软件工程
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2013-02-01
- 文件大小：
- 199kb
- 下载次数：
- 0次
- 提 供 者：
- zhang******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
led流水灯工程，方便大家好好的学习FPGA-led light water engineering, facilitate proper learning FPGA
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下载文件列表
ledflow
.......\db
.......\..\ledflow.db_info
.......\..\ledflow.sld_design_entry.sci
.......\..\logic_util_heursitic.dat
.......\..\prev_cmp_ledflow.qmsg
.......\incremental_db
.......\..............\compiled_partitions
.......\..............\...................\ledflow.db_info
.......\..............\README
.......\ledflow.asm.rpt
.......\ledflow.bsf
.......\ledflow.done
.......\ledflow.eda.rpt
.......\ledflow.fit - 副本.smsg
.......\ledflow.fit.rpt
.......\ledflow.fit.smsg
.......\ledflow.fit.summary
.......\ledflow.flow.rpt
.......\ledflow.map.rpt
.......\ledflow.map.summary
.......\ledflow.out.sdc
.......\ledflow.pin
.......\ledflow.pof
.......\ledflow.pow.rpt
.......\ledflow.pow.summary
.......\ledflow.qpf
.......\ledflow.qsf
.......\ledflow.qws
.......\ledflow.sdc
.......\ledflow.sof
.......\ledflow.sta.rpt
.......\ledflow.sta.summary
.......\ledflow.v
.......\ledflow.v.bak
.......\ledflow_assignment_defaults.qdf
.......\ledflow_nativelink_simulation.rpt
.......\simulation
.......\..........\modelsim
.......\..........\........\gate_work
.......\..........\........\.........\ledflow
.......\..........\........\.........\.......\verilog.prw
.......\..........\........\.........\.......\verilog.psm
.......\..........\........\.........\.......\_primary.dat
.......\..........\........\.........\.......\_primary.dbs
.......\..........\........\.........\.......\_primary.vhd
.......\..........\........\.........\ledflow_vlg_tst
.......\..........\........\.........\...............\verilog.prw
.......\..........\........\.........\...............\verilog.psm
.......\..........\........\.........\...............\_primary.dat
.......\..........\........\.........\...............\_primary.dbs
.......\..........\........\.........\...............\_primary.vhd
.......\..........\........\.........\_info
.......\..........\........\.........\_temp
.......\..........\........\.........\_vmake
.......\..........\........\ledflow.cr.mti
.......\..........\........\ledflow.mpf
.......\..........\........\ledflow.sft
.......\..........\........\ledflow.vo
.......\..........\........\ledflow.vt
.......\..........\........\ledflow.vt.bak
.......\..........\........\ledflow_fast.vo
.......\..........\........\ledflow_modelsim.xrf
.......\..........\........\ledflow_run_msim_gate_verilog.do
.......\..........\........\ledflow_run_msim_rtl_verilog.do
.......\..........\........\ledflow_run_msim_rtl_verilog.do.bak
.......\..........\........\ledflow_v.sdo
.......\..........\........\ledflow_v.sdo_typ.csd
.......\..........\........\ledflow_v_fast.sdo
.......\..........\........\ledf_low.cr.mti
.......\..........\........\modelsim.ini
.......\..........\........\msim_transcript
.......\..........\........\rtl_work
.......\..........\........\........\ledflow
.......\..........\........\........\.......\verilog.prw
.......\..........\........\........\.......\verilog.psm
.......\..........\........\........\.......\_primary.dat
.......\..........\........\........\.......\_primary.dbs
.......\..........\........\........\.......\_primary.vhd
.......\..........\........\........\ledflow_vlg_tst
.......\..........\........\........\...............\verilog.prw
.......\..........\........\........\...............\verilog.psm
.......\..........\........\........\...............\_primary.dat
.......\..........\........\........\...............\_primary.dbs
.......\..........\........\........\...............\_primary.vhd
.......\..........\........\........\_info
.......\..........\........\........\_temp
.......\..........\........\........\_vmake
.......\..........\........\transcript
.......\..........\........\vsim.wlf
.......\..........\........\work
.......\..........\........\....\ledflow
.......\..........\........\....\.......\verilog.prw
.......\..........\........\....\.......\verilog.psm
.......\..........\........\....\.......\_primary.dat
.......\..........\........\....\.......\_primary.dbs
.......\..........\........\....\.......\_primary.vhd
.......\..........\........\....\ledflow_vlg_tst
.......\..........\........\....\..