文件名称:sick_room_call
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数字电路课程设计题目：病房呼叫系统的FPGA实现。实现了题目要求：支持呼叫记忆功能，有呼叫优先级，护士值班室可给予病房呼叫响应信号。-Digital Circuit Design Title: FPGA implementation of the ward call system. The subject of the request: support call memory function, call priority, nurse duty room can give the ward call response signal.
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下载文件列表
sick_room_call\alarm.v
..............\alarm.v.bak
..............\db\logic_util_heursitic.dat
..............\..\prev_cmp_SRCall.qmsg
..............\..\SRCall.amm.cdb
..............\..\SRCall.asm.qmsg
..............\..\SRCall.asm.rdb
..............\..\SRCall.cbx.xml
..............\..\SRCall.cmp.bpm
..............\..\SRCall.cmp.cbp
..............\..\SRCall.cmp.cdb
..............\..\SRCall.cmp.hdb
..............\..\SRCall.cmp.kpt
..............\..\SRCall.cmp.logdb
..............\..\SRCall.cmp.rdb
..............\..\SRCall.cmp0.ddb
..............\..\SRCall.cmp_merge.kpt
..............\..\SRCall.db_info
..............\..\SRCall.eda.qmsg
..............\..\SRCall.fit.qmsg
..............\..\SRCall.hier_info
..............\..\SRCall.hif
..............\..\SRCall.idb.cdb
..............\..\SRCall.lpc.html
..............\..\SRCall.lpc.rdb
..............\..\SRCall.lpc.txt
..............\..\SRCall.map.bpm
..............\..\SRCall.map.cbp
..............\..\SRCall.map.cdb
..............\..\SRCall.map.hdb
..............\..\SRCall.map.kpt
..............\..\SRCall.map.logdb
..............\..\SRCall.map.qmsg
..............\..\SRCall.map_bb.cdb
..............\..\SRCall.map_bb.hdb
..............\..\SRCall.map_bb.logdb
..............\..\SRCall.mif_update.qmsg
..............\..\SRCall.pre_map.cdb
..............\..\SRCall.pre_map.hdb
..............\..\SRCall.rpp.qmsg
..............\..\SRCall.rtlv.hdb
..............\..\SRCall.rtlv_sg.cdb
..............\..\SRCall.rtlv_sg_swap.cdb
..............\..\SRCall.sgate.rvd
..............\..\SRCall.sgate_sm.rvd
..............\..\SRCall.sgdiff.cdb
..............\..\SRCall.sgdiff.hdb
..............\..\SRCall.sld_design_entry.sci
..............\..\SRCall.sld_design_entry_dsc.sci
..............\..\SRCall.smart_action.txt
..............\..\SRCall.sta.qmsg
..............\..\SRCall.sta.rdb
..............\..\SRCall.sta_cmp.8_slow.tdb
..............\..\SRCall.syn_hier_info
..............\..\SRCall.tan.qmsg
..............\..\SRCall.taw.rdb
..............\..\SRCall.tis_db_list.ddb
..............\..\SRCall.tmw_info
..............\display.v
..............\displayl.v.bak
..............\greybox_tmp\cbx_args.txt
..............\incremental_db\compiled_partitions\SRCall.db_info
..............\..............\...................\SRCall.root_partition.cmp.cdb
..............\..............\...................\SRCall.root_partition.cmp.dfp
..............\..............\...................\SRCall.root_partition.cmp.hdb
..............\..............\...................\SRCall.root_partition.cmp.kpt
..............\..............\...................\SRCall.root_partition.cmp.logdb
..............\..............\...................\SRCall.root_partition.cmp.rcfdb
..............\..............\...................\SRCall.root_partition.cmp.re.rcfdb
..............\..............\...................\SRCall.root_partition.map.cdb
..............\..............\...................\SRCall.root_partition.map.dpi
..............\..............\...................\SRCall.root_partition.map.hdb
..............\..............\...................\SRCall.root_partition.map.kpt
..............\..............\README
..............\latch.v.bak
..............\Lth.v
..............\Lth.v.bak
..............\priority_encoding.v
..............\priority_encoding.v.bak
..............\rea_1to8.v
..............\rea_1to8.v.bak
..............\rst_1to8.v
..............\rst_1to8.v.bak
..............\simulation\modelsim\alarm.vt
..............\..........\........\alarm.vt.bak
..............\..........\........\Lth.vt
..............\..........\........\Lth.vt.bak
..............\..........\........\modelsim.ini
..............\..........\........\msim_transcript
..............\..........\........\priority_encoding.vt
..............\..........\........\priority_encoding.vt.bak
..............\..........\........\rea_1to8.vt
..............\..........\........\rea_1to8.vt.bak
..............\..........\........\rst_1to8.vt
..............\..........\........\rst_1to8.vt.bak
..............\..........\........\.tl_work\rea_1to8\verilog.prw
..............\..........\........\......