文件名称:digital-Timer
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数字时钟，使用Verilog实现，已经调试过了-Digital clock, using Verilog implementation
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下载文件列表
digital Timer
.............\clock.asm.rpt
.............\clock.cdf
.............\clock.done
.............\clock.dpf
.............\clock.fit.eqn
.............\clock.fit.rpt
.............\clock.fit.smsg
.............\clock.fit.summary
.............\clock.flow.rpt
.............\clock.map.eqn
.............\clock.map.rpt
.............\clock.map.summary
.............\clock.pin
.............\clock.pof
.............\clock.qpf
.............\clock.qsf
.............\clock.qws
.............\clock.tan.rpt
.............\clock.tan.summary
.............\clock.v
.............\clock.v.bak
.............\clock_assignment_defaults.qdf
.............\cmp_state.ini
.............\db
.............\..\add_sub_bph.tdf
.............\..\add_sub_onh.tdf
.............\..\clock.asm.qmsg
.............\..\clock.asm_labs.ddb
.............\..\clock.cbx.xml
.............\..\clock.cmp.cdb
.............\..\clock.cmp.hdb
.............\..\clock.cmp.kpt
.............\..\clock.cmp.logdb
.............\..\clock.cmp.rdb
.............\..\clock.cmp.tdb
.............\..\clock.cmp0.ddb
.............\..\clock.dbp
.............\..\clock.db_info
.............\..\clock.eco.cdb
.............\..\clock.fit.qmsg
.............\..\clock.hier_info
.............\..\clock.hif
.............\..\clock.map.cdb
.............\..\clock.map.hdb
.............\..\clock.map.logdb
.............\..\clock.map.qmsg
.............\..\clock.pre_map.cdb
.............\..\clock.pre_map.hdb
.............\..\clock.psp
.............\..\clock.rtlv.hdb
.............\..\clock.rtlv_sg.cdb
.............\..\clock.rtlv_sg_swap.cdb
.............\..\clock.sgdiff.cdb
.............\..\clock.sgdiff.hdb
.............\..\clock.signalprobe.cdb
.............\..\clock.sld_design_entry.sci
.............\..\clock.sld_design_entry_dsc.sci
.............\..\clock.syn_hier_info
.............\..\clock.tan.qmsg
.............\..\clock_cmp.qrpt