文件名称:choose8_1

  • 所属分类:
  • 按钮控件
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2013-01-18
  • 文件大小:
  • 150kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • shao****
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

8选一选择器的verilog实现,运行通过仿真!-8 election selector verilog implementation, running through simulation!
(系统自动生成,下载前可以参看下载内容)

下载文件列表





choose8_1

.........\choose8_1.done

.........\choose8_1.eda.rpt

.........\choose8_1.flow.rpt

.........\choose8_1.map.rpt

.........\choose8_1.map.smsg

.........\choose8_1.map.summary

.........\choose8_1.qpf

.........\choose8_1.qsf

.........\choose8_1.v

.........\choose8_1.v.bak

.........\choose8_1_nativelink_simulation.rpt

.........\db

.........\..\choose8_1.atom_map.rvd

.........\..\choose8_1.cbx.xml

.........\..\choose8_1.cmp.rdb

.........\..\choose8_1.cmp_merge.kpt

.........\..\choose8_1.db_info

.........\..\choose8_1.eda.qmsg

.........\..\choose8_1.hier_info

.........\..\choose8_1.hif

.........\..\choose8_1.lpc.html

.........\..\choose8_1.lpc.rdb

.........\..\choose8_1.lpc.txt

.........\..\choose8_1.map.bpm

.........\..\choose8_1.map.cdb

.........\..\choose8_1.map.hdb

.........\..\choose8_1.map.kpt

.........\..\choose8_1.map.logdb

.........\..\choose8_1.map.qmsg

.........\..\choose8_1.map_bb.cdb

.........\..\choose8_1.map_bb.hdb

.........\..\choose8_1.map_bb.logdb

.........\..\choose8_1.pre_map.cdb

.........\..\choose8_1.pre_map.hdb

.........\..\choose8_1.rpp.qmsg

.........\..\choose8_1.rtlv.hdb

.........\..\choose8_1.rtlv_sg.cdb

.........\..\choose8_1.rtlv_sg_swap.cdb

.........\..\choose8_1.sgate.rvd

.........\..\choose8_1.sgate_sm.rvd

.........\..\choose8_1.sgdiff.cdb

.........\..\choose8_1.sgdiff.hdb

.........\..\choose8_1.sld_design_entry.sci

.........\..\choose8_1.sld_design_entry_dsc.sci

.........\..\choose8_1.smart_action.txt

.........\..\choose8_1.syn_hier_info

.........\..\choose8_1.tis_db_list.ddb

.........\..\choose8_1.tmw_info

.........\..\logic_util_heursitic.dat

.........\..\prev_cmp_choose8_1.qmsg

.........\incremental_db

.........\..............\README

.........\..............\compiled_partitions

.........\..............\...................\choose8_1.db_info

.........\..............\...................\choose8_1.root_partition.map.cdb

.........\..............\...................\choose8_1.root_partition.map.dpi

.........\..............\...................\choose8_1.root_partition.map.hbdb.cdb

.........\..............\...................\choose8_1.root_partition.map.hbdb.hb_info

.........\..............\...................\choose8_1.root_partition.map.hbdb.hdb

.........\..............\...................\choose8_1.root_partition.map.hbdb.sig

.........\..............\...................\choose8_1.root_partition.map.hdb

.........\..............\...................\choose8_1.root_partition.map.kpt

.........\simulation

.........\..........\modelsim

.........\..........\........\choose8_1.vt

.........\..........\........\choose8_1.vt.bak

.........\..........\........\choose8_1_run_msim_rtl_verilog.do

.........\..........\........\choose8_1_run_msim_rtl_verilog.do.bak

.........\..........\........\choose8_1_run_msim_rtl_verilog.do.bak1

.........\..........\........\choose8_1_run_msim_rtl_verilog.do.bak2

.........\..........\........\choose8_1_run_msim_rtl_verilog.do.bak3

.........\..........\........\modelsim.ini

.........\..........\........\msim_transcript

.........\..........\........\rtl_work

.........\..........\........\........\_info

.........\..........\........\........\_temp

.........\..........\........\........\_vmake

.........\..........\........\........\choose8_1

.........\..........\........\........\.........\_primary.dat

.........\..........\........\........\.........\_primary.dbs

.........\..........\........\........\.........\_primary.vhd

.........\..........\........\........\.........\verilog.prw

.........\..........\........\........\.........\verilog.psm

.........\..........\........\........\choose8_1_vlg_tst

.........\..........\........\........\.................\_primary.dat

.........\..........\........\........\.................\_primary.dbs

.........\..........\........\........\.................\_primary.vhd

.........\..........\........\........\.................\verilog.prw

.........\..........\........\........\.................\verilog.psm

.........\..........\........\vsim.wlf

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