文件名称:uart
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基于verilogHDL实现的UART收发，带FIFO缓存。-UART transceiver, with a FIFO buffer.
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下载文件列表
uart
....\uart_fifo_design
....\................\fifo_uart.bsf
....\................\fifo_uart.qip
....\................\fifo_uart.v
....\................\fifo_uart_bb.v
....\................\fifo_uart_wave0.jpg
....\................\fifo_uart_wave1.jpg
....\................\fifo_uart_waveforms.html
....\................\src
....\................\...\clk_generator.v
....\................\...\clk_generator.v.bak
....\................\...\fifo_read_write.v
....\................\...\fifo_read_write.v.bak
....\................\...\key_scan.v
....\................\...\key_scan.v.bak
....\................\...\system_ctrl.v
....\................\...\system_ctrl.v.bak
....\................\...\transcript
....\................\...\uart_fifo_design.v
....\................\...\uart_fifo_design.v.bak
....\................\...\uart_receiver.v
....\................\...\uart_receiver.v.bak
....\................\...\uart_transfer.v
....\................\...\uart_transfer.v.bak
....\................\uart_fifo_design.asm.rpt
....\................\uart_fifo_design.cdf
....\................\uart_fifo_design.done
....\................\uart_fifo_design.dpf
....\................\uart_fifo_design.fit.rpt
....\................\uart_fifo_design.fit.smsg
....\................\uart_fifo_design.fit.summary
....\................\uart_fifo_design.flow.rpt
....\................\uart_fifo_design.map.rpt
....\................\uart_fifo_design.map.summary
....\................\uart_fifo_design.pin
....\................\uart_fifo_design.pof
....\................\uart_fifo_design.qpf
....\................\uart_fifo_design.qsf
....\................\uart_fifo_design.qws
....\................\uart_fifo_design.sim.rpt
....\................\uart_fifo_design.sof
....\................\uart_fifo_design.sta.rpt
....\................\uart_fifo_design.sta.summary
....\................\uart_fifo_design.tan.rpt
....\................\uart_fifo_design.tan.summary
....\................\uart_fifo_design.tcl
....\................\uart_fifo_design.tcl.bak
....\................\uart_fifo_design.vwf
....\uart_io_test
....\............\db
....\............\output_file.jic
....\............\output_file.map
....\............\src
....\............\...\clk_generator.v
....\............\...\clk_generator.v.bak
....\............\...\system_ctrl.v
....\............\...\system_ctrl.v.bak
....\............\...\uart_io_test.v
....\............\...\uart_io_test.v.bak
....\............\...\uart_receiver.v
....\............\...\uart_receiver.v.bak
....\............\...\uart_transfer.v
....\............\...\uart_transfer.v.bak
....\............\uart_io_test.asm.rpt
....\............\uart_io_test.cdf
....\............\uart_io_test.done
....\............\uart_io_test.dpf
....\............\uart_io_test.fit.rpt
....\............\uart_io_test.fit.smsg
....\............\uart_io_test.fit.summary
....\............\uart_io_test.flow.rpt
....\............\uart_io_test.map.rpt
....\............\uart_io_test.map.summary
....\............\uart_io_test.pin
....\............\uart_io_test.pof
....\............\uart_io_test.qpf
....\............\uart_io_test.qsf
....\............\uart_io_test.qws
....\............\uart_io_test.sof
....\............\uart_io_test.tan.rpt
....\............\uart_io_test.tan.summary
....\............\uart_io_test.tcl
....\............\uart_io_test.tcl.bak
....\............\uart_io_test_assignment_defaults.qdf
....\wxp