文件名称:bps
介绍说明－－下载内容均来自于网络，请自行研究使用
ＦＰＧＡ的运用：基于ｖｅｒｉｌｏｇ的任意波特率配置模块-The application of FPGA: Based on Verilog arbitrary baud rate configuration module
(系统自动生成,下载前可以参看下载内容)
下载文件列表
.sopc_builder
.............\filters.xml
.............\preferences.xml
bps.asm.rpt
bps.done
bps.dpf
bps.eda.rpt
bps.fit.rpt
bps.fit.smsg
bps.fit.summary
bps.flow.rpt
bps.map.rpt
bps.map.summary
bps.pin
bps.pof
bps.qpf
bps.qsf
bps.qws
bps.sim.rpt
bps.sof
bps.sta.rpt
bps.sta.summary
bps.tan.rpt
bps.tan.summary
bps.v
bps.v.bak
bps.vwf
bps_assignment_defaults.qdf
bps_nativelink_simulation.rpt
db
..\bps.cbx.xml
..\bps.cmp.rdb
..\bps.db_info
..\bps.eco.cdb
..\bps.hier_info
..\bps.hif
..\bps.lpc.html
..\bps.lpc.rdb
..\bps.lpc.txt
..\bps.map.ecobp
..\bps.map.kpt
..\bps.map.qmsg
..\bps.map_bb.cdb
..\bps.map_bb.hdb
..\bps.map_bb.logdb
..\bps.pre_map.cdb
..\bps.pre_map.hdb
..\bps.rtlv.hdb
..\bps.rtlv_sg.cdb
..\bps.rtlv_sg_swap.cdb
..\bps.sgdiff.cdb
..\bps.sgdiff.hdb
..\bps.sim.cvwf
..\bps.sld_design_entry.sci
..\bps.sld_design_entry_dsc.sci
..\bps.syn_hier_info
..\bps.tis_db_list.ddb
..\logic_util_heursitic.dat
..\prev_cmp_bps.asm.qmsg
..\prev_cmp_bps.eda.qmsg
..\prev_cmp_bps.fit.qmsg
..\prev_cmp_bps.map.qmsg
..\prev_cmp_bps.qmsg
..\prev_cmp_bps.sim.qmsg
..\prev_cmp_bps.tan.qmsg
..\wed.wsf
incremental_db
..............\compiled_partitions
..............\...................\bps.root_partition.cmp.cdb
..............\...................\bps.root_partition.cmp.dfp
..............\...................\bps.root_partition.cmp.hdb
..............\...................\bps.root_partition.cmp.kpt
..............\...................\bps.root_partition.cmp.logdb
..............\...................\bps.root_partition.cmp.rcfdb
..............\...................\bps.root_partition.cmp.re.rcfdb
..............\...................\bps.root_partition.map.atm
..............\...................\bps.root_partition.map.cdb
..............\...................\bps.root_partition.map.dpi
..............\...................\bps.root_partition.map.hdb
..............\...................\bps.root_partition.map.hdbx
..............\...................\bps.root_partition.map.kpt
..............\README
lcd_11.bdf
serv_req_info.txt
simulation
..........\modelsim
..........\........\bps.sft
..........\........\bps.vo
..........\........\bps.vt
..........\........\bps.vt.bak
..........\........\bps_modelsim.xrf
..........\........\bps_run_msim_rtl_verilog.do
..........\........\bps_run_msim_rtl_verilog.do.bak
..........\........\bps_run_msim_rtl_verilog.do.bak1
..........\........\bps_run_msim_rtl_verilog.do.bak10
..........\........\bps_run_msim_rtl_verilog.do.bak11
..........\........\bps_run_msim_rtl_verilog.do.bak2
..........\........\bps_run_msim_rtl_verilog.do.bak3
..........\........\bps_run_msim_rtl_verilog.do.bak4
..........\........\bps_run_msim_rtl_verilog.do.bak5