文件名称:ads1282_code

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 468kb
  • 下载次数:
  • 1次
  • 提 供 者:
  • 陈**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

用VHDL写的控制TI公司32位高精度ADC的程序,可以可靠运行,已经应用于实际项目-Control TI' s 32-bit precision ADC program written using VHDL, reliable operation, has been applied to the actual project
(系统自动生成,下载前可以参看下载内容)

下载文件列表





ads1282_code\lpm_fifo0_wave0.jpg

............\data_o.vhd

............\fifomxn.vhd

............\fp10.vhd

............\fp4.vhd

............\fp40.vhd

............\fp_16.vhd

............\lpm_fifo0.vhd

............\lpm_shiftreg0.vhd

............\mux2.vhd

............\mux2_data.vhd

............\ren_1.vhd

............\ren_d_delay.vhd

............\reset_c.vhd

............\sclk_1.vhd

............\sclk_r.vhd

............\wreq.vhd

............\sclk_1.inc

............\lpm_fifo0_waveforms.html

............\serv_req_info.txt

............\control_1282.bdf

............\control_1282_1.bdf

............\fifo_test.bdf

............\fp40_1.bdf

............\fpga_dsp.bdf

............\fp_40.bdf

............\sp_1282.bdf

............\sync_test.bdf

............\top_1282.bdf

............\top_1282_1.bdf

............\top_test1.bdf

............\data_o.vhd.bak

............\fp40.vhd.bak

............\fp_16.vhd.bak

............\mux2_data.vhd.bak

............\ren_1.vhd.bak

............\ren_d_delay.vhd.bak

............\reset_c.vhd.bak

............\sclk_1.vhd.bak

............\sclk_r.vhd.bak

............\wreq.vhd.bak

............\control_1282.bsf

............\control_1282_1.bsf

............\fp10.bsf

............\fp4.bsf

............\fp40.bsf

............\fp40_1.bsf

............\lpm_fifo0.bsf

............\lpm_shiftreg0.bsf

............\mux2.bsf

............\mux2_data.bsf

............\ren_1.bsf

............\ren_d_delay.bsf

............\reset_c.bsf

............\sclk_1.bsf

............\sclk_r.bsf

............\sp_1282.bsf

............\wreq.bsf

............\ads1282_code.cdf

............\lpm_fifo0.cmp

............\lpm_shiftreg0.cmp

............\ads1282_code.done

............\ads1282_code.dpf

............\ads1282_code.jdi

............\fpga_test.jic

............\sync_test.jic

............\fpga_test.map

............\sync_test.map

............\ads1282_code.pin

............\ads1282_code.pof

............\ads1282_code_assignment_defaults.qdf

............\lpm_fifo0.qip

............\lpm_shiftreg0.qip

............\ads1282_code.qpf

............\ads1282_code.qsf

............\ads1282_code.asm.rpt

............\ads1282_code.fit.rpt

............\ads1282_code.flow.rpt

............\ads1282_code.map.rpt

............\ads1282_code.sim.rpt

............\ads1282_code.tan.rpt

............\ads1282_code.sof

............\control_1282_1.stp

............\ads1282_code.fit.summary

............\ads1282_code.map.summary

............\ads1282_code.tan.summary

............\control_1282.vwf

............\control_1282_1.vwf

............\fifomxn.vwf

............\fifo_test.vwf

............\fp40_1.vwf

............\fp_16.vwf

............\fp_40.vwf

............\mux2.vwf

............\mux2_data.vwf

............\ren_1.vwf

............\ren_d_delay.vwf

............\reset_c.vwf

............\sclk_1.vwf

............\sclk_r.vwf

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