digita_clock\.lso

............\clk_counter.cmd_log

............\clk_counter.lso

............\clk_counter.ngc

............\clk_counter.ngr

............\clk_counter.prj

............\clk_counter.stx

............\clk_counter.syr

............\clk_counter.v

............\clk_counter.xst

............\clk_counter_xst.xrpt

............\clk_gen.bld

............\clk_gen.cmd_log

............\clk_gen.lso

............\clk_gen.ngc

............\clk_gen.ngd

............\clk_gen.ngr

............\clk_gen.prj

............\clk_gen.syr

............\clk_gen.v

............\clk_gen.xst

............\clk_gen_isim_beh.exe

............\clk_gen_ngdbuild.xrpt

............\clk_gen_results.wcfg

............\clk_gen_xst.xrpt

............\clock.bgn

............\clock.bit

............\clock.bld

............\clock.cmd_log

............\clock.drc

............\clock.lso

............\clock.ncd

............\clock.ngc

............\clock.ngd

............\clock.ngr

............\clock.pad

............\clock.par

............\clock.pcf

............\clock.prj

............\clock.ptwx

............\clock.stx

............\clock.syr

............\clock.twr

............\clock.twx

............\clock.unroutes

............\clock.ut

............\clock.v

............\clock.xpi

............\clock.xst

............\clock_bitgen.xwbt

............\clock_div.cmd_log

............\clock_div.lso

............\clock_div.ngc

............\clock_div.ngr

............\clock_div.prj

............\clock_div.stx

............\clock_div.syr

............\clock_div.v

............\clock_div.xst

............\clock_div_isim_beh.exe

............\clock_div_xst.xrpt

............\clock_envsettings.html

............\clock_guide.ncd

............\clock_map.map

............\clock_map.mrp

............\clock_map.ncd

............\clock_map.ngm

............\clock_map.xrpt

............\clock_ngdbuild.xrpt

............\clock_pad.csv

............\clock_pad.txt

............\clock_par.xrpt

............\clock_summary.html

............\clock_summary.xml

............\clock_usage.xml

............\clock_xst.xrpt

............\decoder_7_seg.cmd_log

............\decoder_7_seg.lso

............\decoder_7_seg.ngc

............\decoder_7_seg.ngr

............\decoder_7_seg.prj

............\decoder_7_seg.stx

............\decoder_7_seg.syr

............\decoder_7_seg.v

............\decoder_7_seg.xst

............\decoder_7_seg_xst.xrpt

............\digital_clk.ucf

............\digita_clock.gise

............\digita_clock.xise

............\final simulation.wcfg

............\fuse.log

............\ipcore_dir

............\.seconfig\clock.xreport

............\.........\digita_clock.projectmgr

............\iseconfig

............\..im\isim_usage_statistics.html

............\....\tb_clk_isim_beh.exe.sim\isimcrash.log

............\....\.......................\ISimEngine-DesignHierarchy.dbg

............\....\.......................\isimkernel.log

............\....\.......................\netId.dat