文件名称:verilog_UART_100MHZ
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自己写的verilog UART程序,前仿真后仿真,下到板子里都对,ISE的-Verilog UART write your own program, before simulation after simulation, are right next to the plate yard, ISE' s
(系统自动生成,下载前可以参看下载内容)
下载文件列表
UART_divider.v
UART_host.v
UART_top.v
UART_top_tb.v
UART_Transmitter_Arch.v
UART8_Receiver.v