文件名称:02.7Seg_Nexys3
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内容是基于FPGA的VHDL和verilog程序的编写，有助于初学者的学习-The content is based on the FPGA VHDL and Verilog program written to help beginners learning
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下载文件列表
02.7Seg_Nexys3\Bitfile\Verilog\7Seg_top.bit
..............\.......\.HDL\7Seg_top.bit
..............\code\Verilog\clock_divider.v
..............\....\.......\counter.v
..............\....\.......\main.v
..............\....\.......\myucf.ucf
..............\....\.......\seven_seg_controller.v
..............\....\.......\state_machine.v
..............\....\.HDL\clock_divider.vhd
..............\....\....\counter.vhd
..............\....\....\main.vhd
..............\....\....\myucf.ucf
..............\....\....\seven_seg_controller.vhd
..............\....\....\state_machine.vhd
..............\doc\Timer with millisecond precision.doc
..............\Nexys3_Seven_Seg_Demo.pdf
..............\project\Verilog\Nexys3_Seven_Seg_Demo\Nexys3_Seven_Seg_Demo.xise
..............\.......\.HDL\Nexys3_Seven_Seg_Semo\Nexys3_seven_seg_demo.xise
..............\.......\.erilog\Nexys3_Seven_Seg_Demo
..............\.......\.HDL\Nexys3_Seven_Seg_Semo
..............\Bitfile\Verilog
..............\.......\VHDL
..............\code\Verilog
..............\....\VHDL
..............\project\Verilog
..............\.......\VHDL
..............\Bitfile
..............\code
..............\doc
..............\project
02.7Seg_Nexys3
..............\.......\.HDL\7Seg_top.bit
..............\code\Verilog\clock_divider.v
..............\....\.......\counter.v
..............\....\.......\main.v
..............\....\.......\myucf.ucf
..............\....\.......\seven_seg_controller.v
..............\....\.......\state_machine.v
..............\....\.HDL\clock_divider.vhd
..............\....\....\counter.vhd
..............\....\....\main.vhd
..............\....\....\myucf.ucf
..............\....\....\seven_seg_controller.vhd
..............\....\....\state_machine.vhd
..............\doc\Timer with millisecond precision.doc
..............\Nexys3_Seven_Seg_Demo.pdf
..............\project\Verilog\Nexys3_Seven_Seg_Demo\Nexys3_Seven_Seg_Demo.xise
..............\.......\.HDL\Nexys3_Seven_Seg_Semo\Nexys3_seven_seg_demo.xise
..............\.......\.erilog\Nexys3_Seven_Seg_Demo
..............\.......\.HDL\Nexys3_Seven_Seg_Semo
..............\Bitfile\Verilog
..............\.......\VHDL
..............\code\Verilog
..............\....\VHDL
..............\project\Verilog
..............\.......\VHDL
..............\Bitfile
..............\code
..............\doc
..............\project
02.7Seg_Nexys3