文件名称:pllVerilogCode
介绍说明－－下载内容均来自于网络，请自行研究使用
this relaxation of mind in moody session-this is relaxation of mind in moody session
(系统自动生成,下载前可以参看下载内容)
下载文件列表
LockDetectorV2.v
PlaceLabel.m
PLL.v
pll_input_abs.dat
pll_output_abs.dat
pll_output_rel.dat
ReadSimulationData.m
Register.v
reinvoke.swe
RSFFx4.v
Serializer.v
SerializerAndPLLv2.v
ShiftRegister.v
SimpleClock40MHz.v
test_ClockDivider.v
test_ClockGenerator.v
test_DivideBy2.v
test_Jitter.v
test_PLL.v
test_Serializer.v
test_SerializerAndPLL.v
test_ShiftRegister.v
test_ThreeStatePD.v
test_VCO.v
ThreeStatePD.v
VCO.v
ChargePump.v
ClockDivider.v
ClockGenerator.v
ClockSource.v
DisplayData.m
DivideBy2.v
JitterProbe.v
PlaceLabel.m
PLL.v
pll_input_abs.dat
pll_output_abs.dat
pll_output_rel.dat
ReadSimulationData.m
Register.v
reinvoke.swe
RSFFx4.v
Serializer.v
SerializerAndPLLv2.v
ShiftRegister.v
SimpleClock40MHz.v
test_ClockDivider.v
test_ClockGenerator.v
test_DivideBy2.v
test_Jitter.v
test_PLL.v
test_Serializer.v
test_SerializerAndPLL.v
test_ShiftRegister.v
test_ThreeStatePD.v
test_VCO.v
ThreeStatePD.v
VCO.v
ChargePump.v
ClockDivider.v
ClockGenerator.v
ClockSource.v
DisplayData.m
DivideBy2.v
JitterProbe.v