可编程逻辑器件CPLD/FPGA 该实验系统采用了独特的设计技术，使得实验用的可编程CPLD/FPGA 器件的I/O 接口与系统的相关器件采用固定连接-The programmable logic device CPLD/FPGA The experimental system uses a unique design technology, making the experiment with the programmable CPLD/FPGA device I/O interface with the system devices with a fixed connection