文件名称:v91SysGen
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audio program in spartan6 FPGA
(系统自动生成,下载前可以参看下载内容)
下载文件列表
v91SysGen\wrapper\netlist\xst\dump.xst\xupv2pro_wrapper.prj\ngx\notopt
.........\.......\.......\...\........\....................\...\opt
.........\.......\.......\...\........\....................\ngx
.........\chipscope\loopback\audio_xupv2p\sysgen\_xmsgs
.........\wrapper\netlist\xst\dump.xst\xupv2pro_wrapper.prj
.........\.......\.......\...\work\sub00
.........\.......\.......\...\....\vlg56
.........\chipscope\loopback\audio_xupv2p\synth_model
.........\.........\........\............\sysgen
.........\.........\........\............\xflow
.........\.........\........\............\_xmsgs
.........\wrapper\netlist\xst\dump.xst
.........\.......\.......\...\file graph
.........\.......\.......\...\projnav.tmp
.........\.......\.......\...\work
.........\chipscope\loopback\audio_xupv2p
.........\wrapper\Controller\HDL
.........\.......\netlist\templates
.........\.......\.......\xst
.........\.......\.......\_ngo
.........\.......\.......\_xmsgs
.........\chipscope\loopback
.........\Design\jtagcosim
.........\......\reverb
.........\wrapper\Controller
.........\.......\netlist
.........\bsp
.........\chipscope
.........\Design
.........\Docs
.........\issues
.........\SteveA
.........\wrapper
v91SysGen
.........\.......\.......\...\........\....................\...\opt
.........\.......\.......\...\........\....................\ngx
.........\chipscope\loopback\audio_xupv2p\sysgen\_xmsgs
.........\wrapper\netlist\xst\dump.xst\xupv2pro_wrapper.prj
.........\.......\.......\...\work\sub00
.........\.......\.......\...\....\vlg56
.........\chipscope\loopback\audio_xupv2p\synth_model
.........\.........\........\............\sysgen
.........\.........\........\............\xflow
.........\.........\........\............\_xmsgs
.........\wrapper\netlist\xst\dump.xst
.........\.......\.......\...\file graph
.........\.......\.......\...\projnav.tmp
.........\.......\.......\...\work
.........\chipscope\loopback\audio_xupv2p
.........\wrapper\Controller\HDL
.........\.......\netlist\templates
.........\.......\.......\xst
.........\.......\.......\_ngo
.........\.......\.......\_xmsgs
.........\chipscope\loopback
.........\Design\jtagcosim
.........\......\reverb
.........\wrapper\Controller
.........\.......\netlist
.........\bsp
.........\chipscope
.........\Design
.........\Docs
.........\issues
.........\SteveA
.........\wrapper
v91SysGen