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文件名称:vlsimajorprojectlistandabstracts

  • 所属分类：
  • VHDL编程
  • 资源属性：
  • [PDF]
  • 上传时间：
  • 2012-11-26
  • 文件大小：
  • 2.36mb
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  • 0次
  • 提 供 者：
  • siddh*****
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These are the VLSI abstracts.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

vlsimajorprojectlistandabstracts\1 Design and implementation of lossless high speed data compression and Decompression using VHDL.doc

................................\10 Design and implementation of Encryption module for AES core using VERILOG.doc

................................\11 Design and implementation of Decryption module for AES core using VERILOG.doc

................................\12 Design and implementation of Elevator Controller using VHDL.doc

................................\13.Design and implementation of LFSR for low power applications using VERILOG.doc

................................\14 Design and implementation of Serializer and deserializer using VHDL.doc

................................\15 Implementation of Frequency Distributor module using VHDL.doc

................................\16 Design and implementation of Vending machine controller using VHDL.doc

................................\17.Design and implementation of FIR filter using VHDL.doc

................................\18 VLSI design of 8 bit microprocessor implementation using VHDL.doc

................................\19 Design and implementation of array multiplier in VERILOG.doc

................................\2 Design and implementation of Encryption module in DES for SECURITY using VERILOG.doc

................................\20 Design and implementation of state machine controller.doc

................................\21 cam.doc

................................\22 house hold alarm system.doc

................................\23 VLSI design of Reduced Instruction Set Computer Processor core using VHDL.doc

................................\24 VLSI implementation of Memory Core design using VHDL.doc

................................\25.Design and implementation of Random number Generator using VERILOG.doc

................................\3Design and implementation of Decryption module in DES for SECURITY using VERILOG.doc

................................\4.Implementation of real time Candy mechanic using VHDL.doc

................................\5.Design and implementation of pattern generator for circuit under test using VERILOG.doc

................................\6.Efficient design of butterfly architecture for radix 8 fast Fourier transform using VHDL.doc

................................\7 Design and implementation of Digital Code Lock using VHDL.doc

................................\8 Implementation of First in First out (fifo)design using VHDL.doc

................................\9 .VLSI design of Traffic Light Controller using VHDL.doc

................................\brief points.doc

................................\data sheet.pdf

................................\MAJOR projects list for vlsi.doc

................................\New Text Document.txt

................................\vhdl programs lab.doc

vlsimajorprojectlistandabstracts

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