PCI-ip硬件描述语言-开源的，可以做参考设计，如果需要的话，-This models are written in VHDL!

Author is Ovidiu Lupas!



MASTER model

generates PCI compliant signals

checks Target signal compliance with PCI

checks data received from Target for correctness

generates assertion reports if Target signals are not PCI compliant



TARGET model

generates PCI compliant signals

checks Master signal compliance with PCI

checks data received from Master for correctness

generates assertion reports if Master signals are not PCI compliant



Descr iption

The models are boardlevel simulation models and are useful in the testing phase

of

the PCI cores design. The models are 32 bit, 33 MHz PCI compliant but are easy

upgradable to 64 bit, 66 MHz. The models are free　you can redistribute them

and/or modify them under the terms of the GNU General Public License as

published by the Free Software Foundation　either version 2 of the License, or

(at your option) any later version.

The models are distributed in the hope that they will be useful, but WITH