文件名称:tiny64_latest.tar
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Descr iption Tiny64
A 64-Bit RISC CPU with minial resource usage. Every opcode is executed in 2 clock cycles.
The word size is configurable via XLEN from 32 up to the FPGA limit. The assembler supports also
differnet word sizes.
Due simplicity TinyX supports no interrupts, cache, MMU, FPU.
Interrupts may supported in the future.
A 64-Bit RISC CPU with minial resource usage. Every opcode is executed in 2 clock cycles.
The word size is configurable via XLEN from 32 up to the FPGA limit. The assembler supports also
differnet word sizes.
Due simplicity TinyX supports no interrupts, cache, MMU, FPU.
Interrupts may supported in the future.
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7941932tiny64_latest.tar