文件名称:adder_verilog
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This file is a four bit adder verilog code. its function is to add. it has other verilog files as we-This file is a four bit adder verilog code. its function is to add. it has other verilog files as well
(系统自动生成,下载前可以参看下载内容)
下载文件列表
adder_verilog\AdderSubtractor.v
.............\Fadder.v
.............\fourbit_adder.v
.............\full_adder.v
.............\machine.v
.............\seven_seg.v
.............\shiftrne.v
adder_verilog
.............\Fadder.v
.............\fourbit_adder.v
.............\full_adder.v
.............\machine.v
.............\seven_seg.v
.............\shiftrne.v
adder_verilog