文件名称:DDR_CTRL
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DDR Verilog 控制器，quartus 10.1工程。适用Altera Cyclone® III starter board-DDR control quatrus 10.1，Altera Cyclone® III starter board
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下载文件列表
DDR_CTRL\altmemphy-library\auk_ddr_hp_controller.ocp
........\alt_mem_phy_defines.v
........\auk_ddr_hp_controller.ocp
........\auk_ddr_hp_controller.vhd
........\db\DDR_CTRL.db_info
........\..\DDR_CTRL.eco.cdb
........\..\DDR_CTRL.sld_design_entry.sci
........\DDR.bsf
........\DDR.html
........\DDR.ppf
........\DDR.qip
........\DDR.v
........\DDR_advisor.ipa
........\DDR_auk_ddr_hp_controller_wrapper.v
........\DDR_bb.v
........\DDR_controller_phy.v
........\DDR_CTRL.qpf
........\DDR_CTRL.qsf
........\DDR_CTRL.qws
........\DDR_CTRL.v
........\DDR_CTRL.v.bak
........\DDR_example_driver.v
........\DDR_example_top.sdc
........\DDR_example_top.v
........\DDR_ex_lfsr8.v
........\ddr_high_performance_controller-library\auk_ddr_hp_controller.ocp
........\DDR_phy.bsf
........\DDR_phy.html
........\DDR_phy.qip
........\DDR_phy.v
........\DDR_phy_alt_mem_phy.v
........\DDR_phy_alt_mem_phy_pll.qip
........\DDR_phy_alt_mem_phy_pll.v
........\DDR_phy_alt_mem_phy_pll.v_.bak
........\DDR_phy_alt_mem_phy_pll_bb.v
........\DDR_phy_alt_mem_phy_seq.vhd
........\DDR_phy_alt_mem_phy_seq_wrapper.v
........\DDR_phy_bb.v
........\DDR_phy_ddr_pins.tcl
........\DDR_phy_ddr_timing.sdc
........\DDR_phy_report_timing.tcl
........\DDR_pin_assignments.tcl
........\testbench\DDR_example_top_tb.v
........\.........\DDR_example_top_tb.v.tmp
........\.........\DDR_full_mem_model.v
........\.........\DDR_mem_model.v
........\altmemphy-library
........\db
........\ddr_high_performance_controller-library
........\testbench
DDR_CTRL
........\alt_mem_phy_defines.v
........\auk_ddr_hp_controller.ocp
........\auk_ddr_hp_controller.vhd
........\db\DDR_CTRL.db_info
........\..\DDR_CTRL.eco.cdb
........\..\DDR_CTRL.sld_design_entry.sci
........\DDR.bsf
........\DDR.html
........\DDR.ppf
........\DDR.qip
........\DDR.v
........\DDR_advisor.ipa
........\DDR_auk_ddr_hp_controller_wrapper.v
........\DDR_bb.v
........\DDR_controller_phy.v
........\DDR_CTRL.qpf
........\DDR_CTRL.qsf
........\DDR_CTRL.qws
........\DDR_CTRL.v
........\DDR_CTRL.v.bak
........\DDR_example_driver.v
........\DDR_example_top.sdc
........\DDR_example_top.v
........\DDR_ex_lfsr8.v
........\ddr_high_performance_controller-library\auk_ddr_hp_controller.ocp
........\DDR_phy.bsf
........\DDR_phy.html
........\DDR_phy.qip
........\DDR_phy.v
........\DDR_phy_alt_mem_phy.v
........\DDR_phy_alt_mem_phy_pll.qip
........\DDR_phy_alt_mem_phy_pll.v
........\DDR_phy_alt_mem_phy_pll.v_.bak
........\DDR_phy_alt_mem_phy_pll_bb.v
........\DDR_phy_alt_mem_phy_seq.vhd
........\DDR_phy_alt_mem_phy_seq_wrapper.v
........\DDR_phy_bb.v
........\DDR_phy_ddr_pins.tcl
........\DDR_phy_ddr_timing.sdc
........\DDR_phy_report_timing.tcl
........\DDR_pin_assignments.tcl
........\testbench\DDR_example_top_tb.v
........\.........\DDR_example_top_tb.v.tmp
........\.........\DDR_full_mem_model.v
........\.........\DDR_mem_model.v
........\altmemphy-library
........\db
........\ddr_high_performance_controller-library
........\testbench
DDR_CTRL