文件名称:Chapter-4
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- VHDL编程
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- [VHDL] [源码]
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- 2012-11-26
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- 7kb
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Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8.
• Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files.
• Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip”
• The OVL directory has OVL library version 1.0 and its documentations
• In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition.
• In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
• Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files.
• Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip”
• The OVL directory has OVL library version 1.0 and its documentations
• In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition.
• In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
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下载文件列表
Chapter 4\add_1bit.v
.........\add_1bit_blocking.v
.........\add_1bit_f.v
.........\add_1bit_p.v
.........\add_1bit_p2p.v
.........\add_1bit_p_named.v
.........\add_4bit.v
.........\add_4bit_gen.v
.........\add_4bit_genif.v
.........\add_4bit_p2p.v
.........\add_4bit_vec.v
.........\Anding.v
.........\AndingTest.v
.........\maj3_p.v
.........\multi_alu.v
.........\multi_alu_test.v
.........\priority_encoder.v
.........\quad_mux2_1.v
.........\test_add_1bit_blocking.v
.........\test_add_1bit_p.v
.........\test_add_4bit.v
.........\test_maj3_p.v
.........\test_priority_encoder.v
.........\test_quad_mux2_1.v
.........\test_xor3.v
.........\TriMux.v
.........\TriMuxTest.v
.........\xor3_behavioral.v
.........\xor3_p.v
Chapter 4
.........\add_1bit_blocking.v
.........\add_1bit_f.v
.........\add_1bit_p.v
.........\add_1bit_p2p.v
.........\add_1bit_p_named.v
.........\add_4bit.v
.........\add_4bit_gen.v
.........\add_4bit_genif.v
.........\add_4bit_p2p.v
.........\add_4bit_vec.v
.........\Anding.v
.........\AndingTest.v
.........\maj3_p.v
.........\multi_alu.v
.........\multi_alu_test.v
.........\priority_encoder.v
.........\quad_mux2_1.v
.........\test_add_1bit_blocking.v
.........\test_add_1bit_p.v
.........\test_add_4bit.v
.........\test_maj3_p.v
.........\test_priority_encoder.v
.........\test_quad_mux2_1.v
.........\test_xor3.v
.........\TriMux.v
.........\TriMuxTest.v
.........\xor3_behavioral.v
.........\xor3_p.v
Chapter 4