文件名称:Chapter-2
- 所属分类：
- VHDL编程
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 5kb
- 下载次数：
- 0次
- 提 供 者：
- shixi******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8.
• Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files.
• Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip”
• The OVL directory has OVL library version 1.0 and its documentations
• In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition.
• In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
• Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files.
• Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip”
• The OVL directory has OVL library version 1.0 and its documentations
• In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition.
• In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Chapter 2\ALU.v
.........\ALUTester.v
.........\Counter4.v
.........\Counter4Tester.v
.........\Detector110.v
.........\Detector110Tester.v
.........\flop.v
.........\FlopTester.v
.........\MultiplexerA.v
.........\MultiplexerA2to1.v
.........\MultiplexerB.v
.........\MultiplexerC.v
.........\MultiplexerD.v
.........\MultiplexerE.v
.........\MultiplexerTester.v
.........\Mux8.v
.........\Mux8Tester.v
.........\ShiftRegister.v
.........\ShiftRegisterTester.v
.........\Synchronizer.v
.........\SynchronizerTester.v
Chapter 2
.........\ALUTester.v
.........\Counter4.v
.........\Counter4Tester.v
.........\Detector110.v
.........\Detector110Tester.v
.........\flop.v
.........\FlopTester.v
.........\MultiplexerA.v
.........\MultiplexerA2to1.v
.........\MultiplexerB.v
.........\MultiplexerC.v
.........\MultiplexerD.v
.........\MultiplexerE.v
.........\MultiplexerTester.v
.........\Mux8.v
.........\Mux8Tester.v
.........\ShiftRegister.v
.........\ShiftRegisterTester.v
.........\Synchronizer.v
.........\SynchronizerTester.v
Chapter 2