文件名称:verilog6
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用verilog语言编写的VGA显示程序。通过本程序可以学习到VGA显示原理，及如何用verilog语言编写vga显示程序。压缩包内也包含此VGA显示程序的modelsim仿真文件。-Verilog language with the VGA display program. Through this program can learn to VGA Display principles, and how to use the verilog language vga display program. This package also contains compressed VGA display program modelsim simulation files.
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下载文件列表
7----VGA
........\db
........\..\prev_cmp_vga.asm.qmsg
........\..\prev_cmp_vga.eda.qmsg
........\..\prev_cmp_vga.fit.qmsg
........\..\prev_cmp_vga.map.qmsg
........\..\prev_cmp_vga.qmsg
........\..\prev_cmp_vga.tan.qmsg
........\..\vga.asm.qmsg
........\..\vga.asm_labs.ddb
........\..\vga.cbx.xml
........\..\vga.cmp.cdb
........\..\vga.cmp.hdb
........\..\vga.cmp.logdb
........\..\vga.cmp.rdb
........\..\vga.cmp.tdb
........\..\vga.cmp0.ddb
........\..\vga.db_info
........\..\vga.eco.cdb
........\..\vga.eda.qmsg
........\..\vga.fit.qmsg
........\..\vga.hier_info
........\..\vga.hif
........\..\vga.map.cdb
........\..\vga.map.hdb
........\..\vga.map.logdb
........\..\vga.map.qmsg
........\..\vga.pre_map.cdb
........\..\vga.pre_map.hdb
........\..\vga.rtlv.hdb
........\..\vga.rtlv_sg.cdb
........\..\vga.rtlv_sg_swap.cdb
........\..\vga.sgdiff.cdb
........\..\vga.sgdiff.hdb
........\..\vga.signalprobe.cdb
........\..\vga.sld_design_entry.sci
........\..\vga.sld_design_entry_dsc.sci
........\..\vga.syn_hier_info
........\..\vga.tan.qmsg
........\..\vga.tis_db_list.ddb
........\simulation
........\..........\modelsim
........\..........\........\vga.sft
........\..........\........\vga.vo
........\..........\........\vga.vt
........\..........\........\vga.vt.bak
........\..........\........\vga_modelsim.xrf
........\..........\........\vga_v.sdo
........\vga.asm.rpt
........\vga.done
........\vga.eda.rpt
........\vga.fit.rpt
........\vga.fit.smsg
........\vga.fit.summary
........\vga.flow.rpt
........\vga.map.rpt
........\vga.map.summary
........\vga.pin
........\vga.pof
........\vga.qpf
........\vga.qsf
........\vga.qws
........\vga.tan.rpt
........\vga.tan.summary
........\vga.v
........\vga.v.bak
........\db
........\..\prev_cmp_vga.asm.qmsg
........\..\prev_cmp_vga.eda.qmsg
........\..\prev_cmp_vga.fit.qmsg
........\..\prev_cmp_vga.map.qmsg
........\..\prev_cmp_vga.qmsg
........\..\prev_cmp_vga.tan.qmsg
........\..\vga.asm.qmsg
........\..\vga.asm_labs.ddb
........\..\vga.cbx.xml
........\..\vga.cmp.cdb
........\..\vga.cmp.hdb
........\..\vga.cmp.logdb
........\..\vga.cmp.rdb
........\..\vga.cmp.tdb
........\..\vga.cmp0.ddb
........\..\vga.db_info
........\..\vga.eco.cdb
........\..\vga.eda.qmsg
........\..\vga.fit.qmsg
........\..\vga.hier_info
........\..\vga.hif
........\..\vga.map.cdb
........\..\vga.map.hdb
........\..\vga.map.logdb
........\..\vga.map.qmsg
........\..\vga.pre_map.cdb
........\..\vga.pre_map.hdb
........\..\vga.rtlv.hdb
........\..\vga.rtlv_sg.cdb
........\..\vga.rtlv_sg_swap.cdb
........\..\vga.sgdiff.cdb
........\..\vga.sgdiff.hdb
........\..\vga.signalprobe.cdb
........\..\vga.sld_design_entry.sci
........\..\vga.sld_design_entry_dsc.sci
........\..\vga.syn_hier_info
........\..\vga.tan.qmsg
........\..\vga.tis_db_list.ddb
........\simulation
........\..........\modelsim
........\..........\........\vga.sft
........\..........\........\vga.vo
........\..........\........\vga.vt
........\..........\........\vga.vt.bak
........\..........\........\vga_modelsim.xrf
........\..........\........\vga_v.sdo
........\vga.asm.rpt
........\vga.done
........\vga.eda.rpt
........\vga.fit.rpt
........\vga.fit.smsg
........\vga.fit.summary
........\vga.flow.rpt
........\vga.map.rpt
........\vga.map.summary
........\vga.pin
........\vga.pof
........\vga.qpf
........\vga.qsf
........\vga.qws
........\vga.tan.rpt
........\vga.tan.summary
........\vga.v
........\vga.v.bak