文件名称:vhdl-ad9910
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ad9910 DDS板 VHDL源代码，在Cyclone II FPGA上调试通过，主要文件说明：
Filename Function
-----------------------------------------------------
dds_controller.vhd top entity, opcode decoding
ddslib.vhd configuration,opcode definition
dds_serial.vhd parallel to serial decoding
fifo.vhd FIFO megafunction intance
phase_register.vhd phase registers
-ad9910 DDS board VHDL source code, in the Cyclone II FPGA debugging through the main file descr iption: Filename Function----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration, opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers-----------------------------------------------------
Filename Function
-----------------------------------------------------
dds_controller.vhd top entity, opcode decoding
ddslib.vhd configuration,opcode definition
dds_serial.vhd parallel to serial decoding
fifo.vhd FIFO megafunction intance
phase_register.vhd phase registers
-ad9910 DDS board VHDL source code, in the Cyclone II FPGA debugging through the main file descr iption: Filename Function----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration, opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers-----------------------------------------------------
(系统自动生成,下载前可以参看下载内容)
下载文件列表
vhdl-ad9910\.hgtags
...........\.hg_archival.txt
...........\constant.vhd
...........\constant_inst.vhd
...........\db\dds_controller.sim.vwf
...........\..\dds_serial_bus.sim.vwf
...........\ddslib.vhd
...........\dds_controller.cdf
...........\dds_controller.dpf
...........\dds_controller.jdi
...........\dds_controller.pin
...........\dds_controller.qpf
...........\dds_controller.qsf
...........\dds_controller.stp
...........\dds_controller.vhd
...........\dds_controller.vwf
...........\dds_controller_assignment_defaults.qdf
...........\dds_controller_sequencer.vwf
...........\dds_controller_sequencer2.vwf
...........\dds_serial_bus.dpf
...........\dds_serial_bus.pin
...........\dds_serial_bus.qpf
...........\dds_serial_bus.qsf
...........\dds_serial_bus.qws
...........\dds_serial_bus.vhd
...........\dds_serial_bus.vwf
...........\dds_serial_bus_assignment_defaults.qdf
...........\dfs.ptf
...........\dfs.vhd
...........\fifo_mf.vhd
...........\fifo_mf_inst.vhd
...........\LICENSE
...........\make-doc.sh
...........\phase_register.stp
...........\phase_register.vhd
...........\phase_register_orig.vhd
...........\profile_dds.stp
...........\README
...........\test\const1.vhd
...........\....\const1_inst.vhd
...........\....\db\test.sim.vwf
...........\....\test.pin
...........\....\test.qpf
...........\....\test.vwf
...........\TESTLOG
...........\test_lvds_bus.stp
...........\test_lvds_bus.vhd
...........\TODO
...........\V0_1.qsf
...........\V0_1_assignment_defaults.qdf
...........\wrapper\analyzer.vhd
...........\.......\analyzer_inst.vhd
...........\.......\wrapper.pin
...........\.......\wrapper.qpf
...........\.......\wrapper.vhd
...........\test\db
...........\db
...........\test
...........\wrapper
vhdl-ad9910
...........\.hg_archival.txt
...........\constant.vhd
...........\constant_inst.vhd
...........\db\dds_controller.sim.vwf
...........\..\dds_serial_bus.sim.vwf
...........\ddslib.vhd
...........\dds_controller.cdf
...........\dds_controller.dpf
...........\dds_controller.jdi
...........\dds_controller.pin
...........\dds_controller.qpf
...........\dds_controller.qsf
...........\dds_controller.stp
...........\dds_controller.vhd
...........\dds_controller.vwf
...........\dds_controller_assignment_defaults.qdf
...........\dds_controller_sequencer.vwf
...........\dds_controller_sequencer2.vwf
...........\dds_serial_bus.dpf
...........\dds_serial_bus.pin
...........\dds_serial_bus.qpf
...........\dds_serial_bus.qsf
...........\dds_serial_bus.qws
...........\dds_serial_bus.vhd
...........\dds_serial_bus.vwf
...........\dds_serial_bus_assignment_defaults.qdf
...........\dfs.ptf
...........\dfs.vhd
...........\fifo_mf.vhd
...........\fifo_mf_inst.vhd
...........\LICENSE
...........\make-doc.sh
...........\phase_register.stp
...........\phase_register.vhd
...........\phase_register_orig.vhd
...........\profile_dds.stp
...........\README
...........\test\const1.vhd
...........\....\const1_inst.vhd
...........\....\db\test.sim.vwf
...........\....\test.pin
...........\....\test.qpf
...........\....\test.vwf
...........\TESTLOG
...........\test_lvds_bus.stp
...........\test_lvds_bus.vhd
...........\TODO
...........\V0_1.qsf
...........\V0_1_assignment_defaults.qdf
...........\wrapper\analyzer.vhd
...........\.......\analyzer_inst.vhd
...........\.......\wrapper.pin
...........\.......\wrapper.qpf
...........\.......\wrapper.vhd
...........\test\db
...........\db
...........\test
...........\wrapper
vhdl-ad9910