文件名称:exp_micro_s
介绍说明－－下载内容均来自于网络，请自行研究使用
自己在QuartusII9.1及Modelsim新版本中完成的microsequencer实例的工程文件。
1.echo uart,接收rx_data,再回复！
2.运行时请注意完整路径：
D:\EXP\EXP_SOPCbuilder\exp_micro_s
3.UART数据输入问题？
3.1 MODELSIM中w完信号后，run/restart一次。
3.2 设置clock=20ns。
3.3 命令行中输入uart_drive调出uart_in.log窗口。
+号后,输入LOVE CHINA！
3.4 run 1ms.看波形结果。
3.5 quit -f。
ZHJ
2009/11/9 晚-Quartus project file for Classic exp with MICRO-SEQUENCER:echo uart
1.echo uart,接收rx_data,再回复！
2.运行时请注意完整路径：
D:\EXP\EXP_SOPCbuilder\exp_micro_s
3.UART数据输入问题？
3.1 MODELSIM中w完信号后，run/restart一次。
3.2 设置clock=20ns。
3.3 命令行中输入uart_drive调出uart_in.log窗口。
+号后,输入LOVE CHINA！
3.4 run 1ms.看波形结果。
3.5 quit -f。
ZHJ
2009/11/9 晚-Quartus project file for Classic exp with MICRO-SEQUENCER:echo uart
(系统自动生成,下载前可以参看下载内容)
下载文件列表
exp_micro_s\microsequencer.mif
...........\microsequencer.v.bak
...........\exp_micro_s.qpf
...........\exp_micro_s.qsf
...........\sopc_builder_log.txt
...........\microsequencer_hw.tcl
...........\microsequencer.v
...........\sopc_add_qip_file.tcl
...........\MICRO.html
...........\micro_seq.sopc
...........\micro_seq.sopcinfo
...........\micro_seq.html
...........\microsequencer_0.v
...........\micro_seq.qip
...........\micro_seq.ptf
...........\micro_seq.ptf.pre_generation_ptf
...........\micro_seq.ptf.8.0
...........\micro_seq.v
...........\micro_seq.ptf.bak
...........\micro_seq_log.txt
...........\dma.v
...........\onchip_memory.hex
...........\onchip_memory.v
...........\uart.v
...........\micro_seq_inst.v
...........\micro_seq.bsf
...........\micro_seq_generation_script
...........\microsequencer.ver
...........\onchip_memory.ver
...........\exp_micro_s.qws
...........\micro_seq_sim\onchip_memory.dat
...........\.............\contents_file_warning.txt
...........\.............\uart_input_data_stream.dat
...........\.............\uart_input_data_mutex.dat
...........\.............\uart.pl
...........\.............\tail-f.pl
...........\.............\uart_log_module.txt
...........\.............\virtuals.do
...........\.............\wave_presets.do
...........\.............\list_presets.do
...........\.............\setup_sim.do
...........\.............\uart_log.bat
...........\.............\uart_drive.bat
...........\.............\modelsim.tcl
...........\.............\create_micro_seq_project.do
...........\.............\transcript
...........\.............\vsim.wlf
...........\.............\wave.do
...........\.............\uart_in.log
...........\.............\micro_seq_sim.cr.mti
...........\.............\micro_seq_sim.mpf
...........\.............\modelsim.ini
...........\.............\work\_info
...........\.............\....\_vmake
...........\.............\....\test_bench\_primary.vhd
...........\.............\....\..........\verilog.psm
...........\.............\....\..........\_primary.dbs
...........\.............\....\..........\_primary.dat
...........\.............\....\onchip_memory\_primary.vhd
...........\.............\....\.............\verilog.psm
...........\.............\....\.............\_primary.dbs
...........\.............\....\.............\_primary.dat
...........\.............\....\uart\_primary.vhd
...........\.............\....\....\verilog.psm
...........\.............\....\....\_primary.dbs
...........\.............\....\....\_primary.dat
...........\.............\....\...._regs\_primary.vhd
...........\.............\....\.........\verilog.psm
...........\.............\....\.........\_primary.dbs
...........\.............\....\.........\_primary.dat
...........\.............\....\......x\_primary.vhd
...........\.............\....\.......\verilog.psm
...........\.............\....\.......\_primary.dbs
...........\.............\....\.......\_primary.dat
...........\.............\....\......._stimulus_source\_primary.vhd
...........\.............\....\.......................\verilog.psm
...........\.............\....\.......................\_primary.dbs
...........\.............\....\.......................\_primary.dat
...........\.............\....\......................._character_source_rom_module\_primary.vhd
...........\.............\....\...................................................\verilog.psm
...........\.............\....\...................................................\_primary.dbs
...........\.............\....\...................................................\_primary.dat
...........\.............\....\.....tx\_primary.vhd
...........\.............\....\.......\verilog.psm
...........\.............\....\.......\_primary.dbs
...........\.............\....\.......\_primary.dat
...........\.............\....\.....log_module\_primary.vhd
...........\.............\....\...............\verilog.psm
...........\.............\....\...............\_primary.dbs
...........\.............\....\...............\_primary.dat
...........\.............\....\dma\_primary.vhd
..
...........\microsequencer.v.bak
...........\exp_micro_s.qpf
...........\exp_micro_s.qsf
...........\sopc_builder_log.txt
...........\microsequencer_hw.tcl
...........\microsequencer.v
...........\sopc_add_qip_file.tcl
...........\MICRO.html
...........\micro_seq.sopc
...........\micro_seq.sopcinfo
...........\micro_seq.html
...........\microsequencer_0.v
...........\micro_seq.qip
...........\micro_seq.ptf
...........\micro_seq.ptf.pre_generation_ptf
...........\micro_seq.ptf.8.0
...........\micro_seq.v
...........\micro_seq.ptf.bak
...........\micro_seq_log.txt
...........\dma.v
...........\onchip_memory.hex
...........\onchip_memory.v
...........\uart.v
...........\micro_seq_inst.v
...........\micro_seq.bsf
...........\micro_seq_generation_script
...........\microsequencer.ver
...........\onchip_memory.ver
...........\exp_micro_s.qws
...........\micro_seq_sim\onchip_memory.dat
...........\.............\contents_file_warning.txt
...........\.............\uart_input_data_stream.dat
...........\.............\uart_input_data_mutex.dat
...........\.............\uart.pl
...........\.............\tail-f.pl
...........\.............\uart_log_module.txt
...........\.............\virtuals.do
...........\.............\wave_presets.do
...........\.............\list_presets.do
...........\.............\setup_sim.do
...........\.............\uart_log.bat
...........\.............\uart_drive.bat
...........\.............\modelsim.tcl
...........\.............\create_micro_seq_project.do
...........\.............\transcript
...........\.............\vsim.wlf
...........\.............\wave.do
...........\.............\uart_in.log
...........\.............\micro_seq_sim.cr.mti
...........\.............\micro_seq_sim.mpf
...........\.............\modelsim.ini
...........\.............\work\_info
...........\.............\....\_vmake
...........\.............\....\test_bench\_primary.vhd
...........\.............\....\..........\verilog.psm
...........\.............\....\..........\_primary.dbs
...........\.............\....\..........\_primary.dat
...........\.............\....\onchip_memory\_primary.vhd
...........\.............\....\.............\verilog.psm
...........\.............\....\.............\_primary.dbs
...........\.............\....\.............\_primary.dat
...........\.............\....\uart\_primary.vhd
...........\.............\....\....\verilog.psm
...........\.............\....\....\_primary.dbs
...........\.............\....\....\_primary.dat
...........\.............\....\...._regs\_primary.vhd
...........\.............\....\.........\verilog.psm
...........\.............\....\.........\_primary.dbs
...........\.............\....\.........\_primary.dat
...........\.............\....\......x\_primary.vhd
...........\.............\....\.......\verilog.psm
...........\.............\....\.......\_primary.dbs
...........\.............\....\.......\_primary.dat
...........\.............\....\......._stimulus_source\_primary.vhd
...........\.............\....\.......................\verilog.psm
...........\.............\....\.......................\_primary.dbs
...........\.............\....\.......................\_primary.dat
...........\.............\....\......................._character_source_rom_module\_primary.vhd
...........\.............\....\...................................................\verilog.psm
...........\.............\....\...................................................\_primary.dbs
...........\.............\....\...................................................\_primary.dat
...........\.............\....\.....tx\_primary.vhd
...........\.............\....\.......\verilog.psm
...........\.............\....\.......\_primary.dbs
...........\.............\....\.......\_primary.dat
...........\.............\....\.....log_module\_primary.vhd
...........\.............\....\...............\verilog.psm
...........\.............\....\...............\_primary.dbs
...........\.............\....\...............\_primary.dat
...........\.............\....\dma\_primary.vhd
..