文件名称:nios_lcd_3c120

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [MacOS] [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 2.43mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • w*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

FPGA 开发中Nios的LCD空置示例!-Nios FPGA development in the LCD vacant example!
(系统自动生成,下载前可以参看下载内容)

下载文件列表

nios_lcd_3c120\altpllpll.ppf

..............\altpllpll.qip

..............\altpllpll.v

..............\altpllpll_bb.v

..............\alt_mem_phy_defines.v

..............\alt_mem_phy_sequencer.vhd

..............\auk_ddr_hp_controller.ocp

..............\auk_ddr_hp_controller.vhd

..............\board_support.tcl

..............\button_pio.v

..............\common_hpddr_setting.tcl

..............\common_kits_setting.tcl

..............\common_nios2_setting.tcl

..............\common_timequest_setting.tcl

..............\common_tse_setting.tcl

..............\cpu.ocp

..............\cpu.sdc

..............\cpu.v

..............\cpu_bht_ram.mif

..............\cpu_dc_tag_ram.mif

..............\cpu_ddr_1_clock_bridge.v

..............\cpu_ddr_clock_bridge.v

..............\cpu_ic_tag_ram.mif

..............\cpu_jtag_debug_module_sysclk.v

..............\cpu_jtag_debug_module_tck.v

..............\cpu_jtag_debug_module_wrapper.v

..............\cpu_mult_cell.v

..............\cpu_ociram_default_contents.mif

..............\cpu_oci_test_bench.v

..............\cpu_rf_ram_a.mif

..............\cpu_rf_ram_b.mif

..............\cpu_test_bench.v

..............\cycloneIII_3c120_niosII_video.done

..............\cycloneIII_3c120_niosII_video.fit.smsg

..............\cycloneIII_3c120_niosII_video.fit.summary

..............\cycloneIII_3c120_niosII_video.jdi

..............\cycloneIII_3c120_niosII_video.map.smsg

..............\cycloneIII_3c120_niosII_video.map.summary

..............\cycloneIII_3c120_niosII_video.pin

..............\cycloneIII_3c120_niosII_video.qpf

..............\cycloneIII_3c120_niosII_video.qsf

..............\cycloneIII_3c120_niosII_video.qws

..............\cycloneIII_3c120_niosII_video.sdc

..............\cycloneIII_3c120_niosII_video.sof

..............\cycloneIII_3c120_niosII_video.sopc.tcl

..............\cycloneIII_3c120_niosII_video.sta.summary

..............\cycloneIII_3c120_niosII_video.v

..............\cycloneIII_3c120_niosII_video_sopc.bsf

..............\cycloneIII_3c120_niosII_video_sopc.debug.tcl

..............\cycloneIII_3c120_niosII_video_sopc.ptf

..............\cycloneIII_3c120_niosII_video_sopc.ptf.8.0

..............\cycloneIII_3c120_niosII_video_sopc.ptf.bak

..............\cycloneIII_3c120_niosII_video_sopc.ptf.pre_generation_ptf

..............\cycloneIII_3c120_niosII_video_sopc.qip

..............\cycloneIII_3c120_niosII_video_sopc.sopc

..............\cycloneIII_3c120_niosII_video_sopc.sopcinfo

..............\cycloneIII_3c120_niosII_video_sopc.v

..............\cycloneIII_3c120_niosII_video_sopc_clock_0.v

..............\cycloneIII_3c120_niosII_video_sopc_generation_script

..............\cycloneIII_3c120_niosII_video_sopc_log.txt

..............\cycloneIII_3c120_niosII_video_sopc_setup_quartus.tcl

..............\ddr2_sdram.html

..............\ddr2_sdram.ppf

..............\ddr2_sdram.qip

..............\ddr2_sdram.v

..............\ddr2_sdram_1.html

..............\ddr2_sdram_1.ppf

..............\ddr2_sdram_1.qip

..............\ddr2_sdram_1.v

..............\ddr2_sdram_1_advisor.ipa

..............\ddr2_sdram_1_auk_ddr_hp_controller_wrapper.v

..............\ddr2_sdram_1_controller_phy.v

..............\ddr2_sdram_1_example_driver.v

..............\ddr2_sdram_1_example_top.sdc

..............\ddr2_sdram_1_example_top.v

..............\ddr2_sdram_1_ex_lfsr8.v

..............\ddr2_sdram_1_phy.html

..............\ddr2_sdram_1_phy.qip

..............\ddr2_sdram_1_phy.v

..............\ddr2_sdram_1_phy_alt_mem_phy.v

..............\ddr2_sdram_1_phy_alt_mem_phy_pll.ppf

..............\ddr2_sdram_1_phy_alt_mem_phy_pll.qip

..............\ddr2_sdram_1_phy_alt_mem_phy_pll.v

..............\ddr2_sdram_1_phy_alt_mem_phy_pll.v_.bak

..............\ddr2_sdram_1_phy_alt_mem_phy_pll_bb.v

..............\ddr2_sdram_1_phy_alt_mem_phy_sequencer_wrapper.v

..............\ddr2_sdram_1_phy_autodetectedpins.tcl

..............\ddr2_sdram_1_phy_ddr_pins.tcl

..............\ddr2_sdram_1_phy_ddr_timing.sdc

..............\ddr2_sdram_1_phy_report_timing.tcl

..............\ddr2_sdram_1_phy_simgen_init.txt

..............\ddr2_sdram_1_phy_summary.csv

..............\ddr2_sdram_1_pin_assign

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