文件名称:Computer-Architecture-lab2
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计算机组成实验作业2，fpga开发板，verilog语言编写-Composition of experimental work computer 2, fpga development board, verilog language
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09级计组实验_B班_31组_5090309744_谢聪_实验2代码\counter.gise
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...............................................\...........\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
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...............................................\...........\...\...\............\...................\Process-BehavioralSim-
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...............................................\counter.ise
...............................................\counter.ucf
...............................................\counter.v
...............................................\counter.xise
...............................................\countert.v
...............................................\countert_isim_beh.wdb
...............................................\countert_isim_par.wdb
...............................................\counter_1.v
...............................................\counter_guide.ncd
...............................................\counter_isim_beh.wdb
...............................................\counter_pa.log
...............................................\counter_pa_ports.v
...............................................\counter_summary.html
...............................................\........xdb\tmp\ise\version
...............................................\...........\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject
...............................................\...........\...\...\............\..................\.........\HDProject_StrTbl
...............................................\...........\...\...\............\..................\__stored_object_table__
...............................................\...........\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
...............................................\...........\...\...\............\.........\.......\RunOnce_tcl_StrTbl
...............................................\...........\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
...............................................\...........\...\...\............\................\................\dpm_project_main_StrTbl
...............................................\...........\...\...\............\................Gui\CViewSelector
...............................................\...........\...\...\............\...................\CViewSelector_StrTbl
...............................................\...........\...\...\............\...................\File-SynthesisOnly
...............................................\...........\...\...\............\...................\File-SynthesisOnly_StrTbl
...............................................\...........\...\...\............\...................\Library-SynthesisOnly
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...............................................\...........\...\...\............\...................\Process-BehavioralSim-
...............................................\...........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG
...............................................\...........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG_StrTbl
...............................................\...........\...\...\............\...................\Process-BehavioralSim-_StrTbl
...............................................\...........\...\...\............\...................\Process-PostRouteSim-
...............................................\...........\...\...\............\...................\Process-PostRouteSim-DESUT_VERILOG
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...............................................\...........\...\...\............\...................\Process-PostRouteSim-_StrTbl
...............................................\...........\...\...\............\...................\Process-SynthesisOnly-
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