文件名称:Computer-Architecture-lab4
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计算机组成实验作业4，fpga开发板，verilog语言编写-Composition of experimental computer operating 4, fpga development board, verilog language
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09级计组实验_B班_31组_5090309744_谢聪_实验4代码\ipcore_dir\blk_mem_gen_ds512.pdf
...............................................\..........\datamemory.asy
...............................................\..........\datamemory.gise
...............................................\..........\datamemory.ise
...............................................\..........\datamemory.ncf
...............................................\..........\datamemory.ngc
...............................................\..........\datamemory.sym
...............................................\..........\datamemory.v
...............................................\..........\datamemory.veo
...............................................\..........\datamemory.vhd
...............................................\..........\datamemory.vho
...............................................\..........\datamemory.xco
...............................................\..........\datamemory.xise
...............................................\..........\datamemory_flist.txt
...............................................\..........\datamemory_xmdf.tcl
...............................................\lab4.gise
...............................................\lab4.ise
...............................................\lab4.xise
...............................................\...._xdb\tmp\ise\version
...............................................\........\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject
...............................................\........\...\...\............\..................\.........\HDProject_StrTbl
...............................................\........\...\...\............\..................\__stored_object_table__
...............................................\........\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
...............................................\........\...\...\............\.........\.......\RunOnce_tcl_StrTbl
...............................................\........\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
...............................................\........\...\...\............\................\................\dpm_project_main_StrTbl
...............................................\........\...\...\............\................Gui\CViewSelector
...............................................\........\...\...\............\...................\CViewSelector_StrTbl
...............................................\........\...\...\............\...................\File-SynthesisOnly
...............................................\........\...\...\............\...................\File-SynthesisOnly_StrTbl
...............................................\........\...\...\............\...................\Library-SynthesisOnly
...............................................\........\...\...\............\...................\Library-SynthesisOnly_StrTbl
...............................................\........\...\...\............\...................\Process-BehavioralSim-
...............................................\........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG
...............................................\........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG_StrTbl
...............................................\........\...\...\............\...................\Process-BehavioralSim-DESUT_XCO
...............................................\........\...\...\............\...................\Process-BehavioralSim-DESUT_XCO_StrTbl
...............................................\........\...\...\............\...................\Process-BehavioralSim-_StrTbl
...............................................\........\...\...\............\...................\Process-PostRouteSim-
...............................................\........\...\...\............\...................\Process-PostRouteSim-DESUT_VERILOG
...............................................\........\...\...\............\...................\Process-Pos
...............................................\..........\datamemory.asy
...............................................\..........\datamemory.gise
...............................................\..........\datamemory.ise
...............................................\..........\datamemory.ncf
...............................................\..........\datamemory.ngc
...............................................\..........\datamemory.sym
...............................................\..........\datamemory.v
...............................................\..........\datamemory.veo
...............................................\..........\datamemory.vhd
...............................................\..........\datamemory.vho
...............................................\..........\datamemory.xco
...............................................\..........\datamemory.xise
...............................................\..........\datamemory_flist.txt
...............................................\..........\datamemory_xmdf.tcl
...............................................\lab4.gise
...............................................\lab4.ise
...............................................\lab4.xise
...............................................\...._xdb\tmp\ise\version
...............................................\........\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject
...............................................\........\...\...\............\..................\.........\HDProject_StrTbl
...............................................\........\...\...\............\..................\__stored_object_table__
...............................................\........\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
...............................................\........\...\...\............\.........\.......\RunOnce_tcl_StrTbl
...............................................\........\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
...............................................\........\...\...\............\................\................\dpm_project_main_StrTbl
...............................................\........\...\...\............\................Gui\CViewSelector
...............................................\........\...\...\............\...................\CViewSelector_StrTbl
...............................................\........\...\...\............\...................\File-SynthesisOnly
...............................................\........\...\...\............\...................\File-SynthesisOnly_StrTbl
...............................................\........\...\...\............\...................\Library-SynthesisOnly
...............................................\........\...\...\............\...................\Library-SynthesisOnly_StrTbl
...............................................\........\...\...\............\...................\Process-BehavioralSim-
...............................................\........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG
...............................................\........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG_StrTbl
...............................................\........\...\...\............\...................\Process-BehavioralSim-DESUT_XCO
...............................................\........\...\...\............\...................\Process-BehavioralSim-DESUT_XCO_StrTbl
...............................................\........\...\...\............\...................\Process-BehavioralSim-_StrTbl
...............................................\........\...\...\............\...................\Process-PostRouteSim-
...............................................\........\...\...\............\...................\Process-PostRouteSim-DESUT_VERILOG
...............................................\........\...\...\............\...................\Process-Pos