文件名称:FPGA-and-DS18B20
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FPGA与测温芯片DS18B20的通信实现，用verilog语言编写。有实际验证过的工程，有实验报告，有DS18B20的资料，适合快速了解。-FPGA chip with the DS18B20 temperature achieved with verilog language. Verified with the actual project, there are experimental reports, the DS18B20 data for quick understanding.
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下载文件列表
FPGA与DS18B20\code\ds.v
.............\DS18B20中文资料.pdf
.............\FPGA与DS18B20通信 .pdf
.............\....最终工程\disp.v
.............\............\disp.v.bak
.............\............\ds.v
.............\............\ds.v.bak
.............\............\dvf.v
.............\............\dvf.v.bak
.............\............\temp1.archive.rpt
.............\............\temp1.asm.rpt
.............\............\temp1.done
.............\............\temp1.dpf
.............\............\temp1.fit.rpt
.............\............\temp1.fit.smsg
.............\............\temp1.fit.summary
.............\............\temp1.flow.rpt
.............\............\temp1.map.rpt
.............\............\temp1.map.summary
.............\............\temp1.pin
.............\............\temp1.pof
.............\............\temp1.qar
.............\............\temp1.qarlog
.............\............\temp1.qpf
.............\............\temp1.qsf
.............\............\temp1.qws
.............\............\temp1.sof
.............\............\temp1.tan.rpt
.............\............\temp1.tan.summary
.............\............\temp1.v
.............\............\temp1.v.bak
.............\............\undo_redo.txt
.............\code
.............\FPGA最终工程
FPGA与DS18B20
.............\DS18B20中文资料.pdf
.............\FPGA与DS18B20通信 .pdf
.............\....最终工程\disp.v
.............\............\disp.v.bak
.............\............\ds.v
.............\............\ds.v.bak
.............\............\dvf.v
.............\............\dvf.v.bak
.............\............\temp1.archive.rpt
.............\............\temp1.asm.rpt
.............\............\temp1.done
.............\............\temp1.dpf
.............\............\temp1.fit.rpt
.............\............\temp1.fit.smsg
.............\............\temp1.fit.summary
.............\............\temp1.flow.rpt
.............\............\temp1.map.rpt
.............\............\temp1.map.summary
.............\............\temp1.pin
.............\............\temp1.pof
.............\............\temp1.qar
.............\............\temp1.qarlog
.............\............\temp1.qpf
.............\............\temp1.qsf
.............\............\temp1.qws
.............\............\temp1.sof
.............\............\temp1.tan.rpt
.............\............\temp1.tan.summary
.............\............\temp1.v
.............\............\temp1.v.bak
.............\............\undo_redo.txt
.............\code
.............\FPGA最终工程
FPGA与DS18B20