文件名称:ecpu_alu
- 所属分类：
- VHDL编程
- 资源属性：
- [C/C++] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 1.63mb
- 下载次数：
- 0次
- 提 供 者：
- Ali K*****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
This a code describing the arithematic logic unit of any device. It performs operations such as addition subtraction and logic operations too. It is coded in verilog.-This is a code describing the arithematic logic unit of any device. It performs operations such as addition subtraction and logic operations too. It is coded in verilog.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ecpu_alu\trunk\adder\alu_adder.v
........\.....\.lu\README
........\.....\...\rtl\verilog\alu.v
........\.....\...\...\.......\alu_barrel_shifter.v
........\.....\...\...\.......\alu_controller.v
........\.....\...\...\.......\alu_controller.vh
........\.....\...\...\.......\alu_datapath.v
........\.....\...\...\.......\alu_datapath.working_nosynth.v
........\.....\...\...\.......\veriwell.key
........\.....\...\...\.......\veriwell.log
........\.....\...\...\.hdl\alu.vhd
........\.....\...\...\....\alu_adder.vhd
........\.....\...\...\....\alu_analog_cadence_tb.vhd
........\.....\...\...\....\alu_analog_tb.vhd
........\.....\...\...\....\alu_barrel_shifter.vhd
........\.....\...\...\....\alu_barrel_shifter_tb.vhd
........\.....\...\...\....\alu_controller.vhd
........\.....\...\...\....\alu_datapath.vhd
........\.....\...\...\....\alu_from_net.vhd
........\.....\...\...\....\alu_stimulus.vhd
........\.....\...\...\....\alu_tb.vhd
........\.....\...\...\....\alu_test.txt
........\.....\...\...\....\compile.simili.files
........\.....\...\...\....\compile_alu.simili.files
........\.....\...\...\....\do_all_simili
........\.....\...\...\....\runit
........\.....\...\scripts\conv_fsm.pl
........\.....\...\setup.sh
........\.....\...\.im\alu_tb.vcd
........\.....\...\...\alu_test.txt
........\.....\...\...\log
........\.....\...\...\runit
........\.....\...\...\run_alu
........\.....\...\.ynth\check_for_synth
........\.....\...\.....\veriwell.key
........\.....\...\.....\veriwell.log
........\.....\...\..stemc\alu_tb.v
........\.....\...\.......\bak\Makefile
........\.....\...\.......\...\verilated.cpp
........\.....\...\.......\gen_systemc.sh
........\.....\...\.......\log
........\.....\...\.......\obj_dir\Makefile
........\.....\...\.......\.......\run.x
........\.....\...\.......\.......\sc_main.cpp
........\.....\...\.......\.......\tracefile.vcd
........\.....\...\.......\.......\Valu_tb.cpp
........\.....\...\.......\.......\Valu_tb.h
........\.....\...\.......\.......\Valu_tb.mk
........\.....\...\.......\.......\Valu_tb_alu_tb.cpp
........\.....\...\.......\.......\Valu_tb_alu_tb.h
........\.....\...\.......\.......\Valu_tb_classes.mk
........\.....\...\.......\.......\Valu_tb__ALLcls.cpp
........\.....\...\.......\.......\Valu_tb__ALLcls.d
........\.....\...\.......\.......\Valu_tb__ALLsup.cpp
........\.....\...\.......\.......\Valu_tb__ALLsup.d
........\.....\...\.......\.......\Valu_tb__Inlines.h
........\.....\...\.......\.......\Valu_tb__Syms.cpp
........\.....\...\.......\.......\Valu_tb__Syms.h
........\.....\...\.......\.......\Valu_tb__ver.d
........\.....\...\.......\.......\Valu_tb__verFiles.dat
........\.....\...\.......\.......\verilated.cpp
........\.....\...\.......\.......\verilog_sc.h
........\.....\...\tb\alu_tb.v
........\.....\barrel_shifter\simple\barrel_shifter_simple.v
........\.....\..............\......\barrel_shifter_simple.working_nosynth.v
........\.....\svn-commit.2.tmp
........\.....\svn-commit.tmp
........\.....\alu\rtl\verilog
........\.....\...\...\vhdl
........\.....\...\systemc\bak
........\.....\...\.......\obj_dir
........\.....\...\rtl
........\.....\...\scripts
........\.....\...\sim
........\.....\...\synth
........\.....\...\systemc
........\.....\...\tb
........\.....\barrel_shifter\other
........\.....\..............\simple
........\.....\adder
........\.....\alu
........\.....\barrel_shifter
........\branches
........\tags
........\trunk
........\web_uploads
ecpu_alu
........\.....\.lu\README
........\.....\...\rtl\verilog\alu.v
........\.....\...\...\.......\alu_barrel_shifter.v
........\.....\...\...\.......\alu_controller.v
........\.....\...\...\.......\alu_controller.vh
........\.....\...\...\.......\alu_datapath.v
........\.....\...\...\.......\alu_datapath.working_nosynth.v
........\.....\...\...\.......\veriwell.key
........\.....\...\...\.......\veriwell.log
........\.....\...\...\.hdl\alu.vhd
........\.....\...\...\....\alu_adder.vhd
........\.....\...\...\....\alu_analog_cadence_tb.vhd
........\.....\...\...\....\alu_analog_tb.vhd
........\.....\...\...\....\alu_barrel_shifter.vhd
........\.....\...\...\....\alu_barrel_shifter_tb.vhd
........\.....\...\...\....\alu_controller.vhd
........\.....\...\...\....\alu_datapath.vhd
........\.....\...\...\....\alu_from_net.vhd
........\.....\...\...\....\alu_stimulus.vhd
........\.....\...\...\....\alu_tb.vhd
........\.....\...\...\....\alu_test.txt
........\.....\...\...\....\compile.simili.files
........\.....\...\...\....\compile_alu.simili.files
........\.....\...\...\....\do_all_simili
........\.....\...\...\....\runit
........\.....\...\scripts\conv_fsm.pl
........\.....\...\setup.sh
........\.....\...\.im\alu_tb.vcd
........\.....\...\...\alu_test.txt
........\.....\...\...\log
........\.....\...\...\runit
........\.....\...\...\run_alu
........\.....\...\.ynth\check_for_synth
........\.....\...\.....\veriwell.key
........\.....\...\.....\veriwell.log
........\.....\...\..stemc\alu_tb.v
........\.....\...\.......\bak\Makefile
........\.....\...\.......\...\verilated.cpp
........\.....\...\.......\gen_systemc.sh
........\.....\...\.......\log
........\.....\...\.......\obj_dir\Makefile
........\.....\...\.......\.......\run.x
........\.....\...\.......\.......\sc_main.cpp
........\.....\...\.......\.......\tracefile.vcd
........\.....\...\.......\.......\Valu_tb.cpp
........\.....\...\.......\.......\Valu_tb.h
........\.....\...\.......\.......\Valu_tb.mk
........\.....\...\.......\.......\Valu_tb_alu_tb.cpp
........\.....\...\.......\.......\Valu_tb_alu_tb.h
........\.....\...\.......\.......\Valu_tb_classes.mk
........\.....\...\.......\.......\Valu_tb__ALLcls.cpp
........\.....\...\.......\.......\Valu_tb__ALLcls.d
........\.....\...\.......\.......\Valu_tb__ALLsup.cpp
........\.....\...\.......\.......\Valu_tb__ALLsup.d
........\.....\...\.......\.......\Valu_tb__Inlines.h
........\.....\...\.......\.......\Valu_tb__Syms.cpp
........\.....\...\.......\.......\Valu_tb__Syms.h
........\.....\...\.......\.......\Valu_tb__ver.d
........\.....\...\.......\.......\Valu_tb__verFiles.dat
........\.....\...\.......\.......\verilated.cpp
........\.....\...\.......\.......\verilog_sc.h
........\.....\...\tb\alu_tb.v
........\.....\barrel_shifter\simple\barrel_shifter_simple.v
........\.....\..............\......\barrel_shifter_simple.working_nosynth.v
........\.....\svn-commit.2.tmp
........\.....\svn-commit.tmp
........\.....\alu\rtl\verilog
........\.....\...\...\vhdl
........\.....\...\systemc\bak
........\.....\...\.......\obj_dir
........\.....\...\rtl
........\.....\...\scripts
........\.....\...\sim
........\.....\...\synth
........\.....\...\systemc
........\.....\...\tb
........\.....\barrel_shifter\other
........\.....\..............\simple
........\.....\adder
........\.....\alu
........\.....\barrel_shifter
........\branches
........\tags
........\trunk
........\web_uploads
ecpu_alu