文件名称:source
介绍说明－－下载内容均来自于网络，请自行研究使用
FPGA驱动八位数码管，做为16进制计数器。-16 counter,using verilog HDL
(系统自动生成,下载前可以参看下载内容)
下载文件列表
source
......\decimal_counter.v
......\decimal_counter.v.bak
......\display.v
......\display.v.bak
......\display_test.v
......\display_test.v.bak
......\DIV_1ms.v
......\DIV_1ms.v.bak
......\DIV_1S.v
......\DIV_1S.v.bak
......\NIXETUBE.tcl
......\Tester.v.bak
......\top.v
......\top.v.bak
......\TopDownDesign.bdf
......\TopDownDesign.bdf.bak
......\TOP_Tester.v
......\TOP_Tester.v.bak
......\decimal_counter.v
......\decimal_counter.v.bak
......\display.v
......\display.v.bak
......\display_test.v
......\display_test.v.bak
......\DIV_1ms.v
......\DIV_1ms.v.bak
......\DIV_1S.v
......\DIV_1S.v.bak
......\NIXETUBE.tcl
......\Tester.v.bak
......\top.v
......\top.v.bak
......\TopDownDesign.bdf
......\TopDownDesign.bdf.bak
......\TOP_Tester.v
......\TOP_Tester.v.bak