文件名称:Reading-User-Data-from-Proms
介绍说明－－下载内容均来自于网络，请自行研究使用
FPGA的配置中，从Flash中读写用户数据，包括VHDL、Verilog程序-in configuring FPGA,reading and writing user data from flash,including the VHDL and Verilog code
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Reading User Data from configuration Proms\readme.txt
..........................................\xapp694_v1_0_archive.zip
..........................................\XAPP694\readme.txt
..........................................\.......\XAPP694_draft_v1_00_0.doc
..........................................\.......\VHDL\readme.txt
..........................................\.......\....\Serial\Source\clock_management.vhd
..........................................\.......\....\......\......\PROM_reader_serial.vhd
..........................................\.......\....\......\......\shift_compare_serial.vhd
..........................................\.......\....\......\.imulation\clock_management.vhd
..........................................\.......\....\......\..........\PROM_reader_serial.vhd
..........................................\.......\....\......\..........\prom_stim_serial.vhd
..........................................\.......\....\......\..........\shift_compare_serial.vhd
..........................................\.......\....\......\..........\sim.do
..........................................\.......\....\......\..........\stimulus_serial.txt
..........................................\.......\....\......\..........\testbench_serial.vhd
..........................................\.......\....\Parallel\Source\clock_management.vhd
..........................................\.......\....\........\......\PROM_reader_parallel.vhd
..........................................\.......\....\........\......\shift_compare_parallel.vhd
..........................................\.......\....\........\.imulation\clock_management.vhd
..........................................\.......\....\........\..........\PROM_reader_parallel.vhd
..........................................\.......\....\........\..........\prom_stim_parallel.vhd
..........................................\.......\....\........\..........\shift_compare_parallel.vhd
..........................................\.......\....\........\..........\sim.do
..........................................\.......\....\........\..........\stimulus_parallel.txt
..........................................\.......\....\........\..........\testbench_parallel.vhd
..........................................\.......\.erilog\readme.txt
..........................................\.......\.......\Serial\Source\clock_management.v
..........................................\.......\.......\......\......\my_LUT2.v
..........................................\.......\.......\......\......\PROM_reader_serial.v
..........................................\.......\.......\......\......\shift_compare_serial.v
..........................................\.......\.......\......\.imulation\clock_management.v
..........................................\.......\.......\......\..........\glbl.v
..........................................\.......\.......\......\..........\my_LUT2.v
..........................................\.......\.......\......\..........\PROM_reader_serial.v
..........................................\.......\.......\......\..........\prom_stim_serial.vhd
..........................................\.......\.......\......\..........\shift_compare_serial.v
..........................................\.......\.......\......\..........\sim.do
..........................................\.......\.......\......\..........\stimulus_serial.txt
..........................................\.......\.......\......\..........\testfixture_serial.v
..........................................\.......\.......\Parallel\Source\clock_management.v
..........................................\.......\.......\........\......\my_LUT2.v
..........................................\.......\.......\........\......\PROM_reader_parallel.v
..........................................\.......\.......\........\......\shift_compare_parallel.v
..........................................\.......\.......\........\.imulation\clock_management.v
..........................................\.......\.......\........\..........\glbl.v
..........................
..........................................\xapp694_v1_0_archive.zip
..........................................\XAPP694\readme.txt
..........................................\.......\XAPP694_draft_v1_00_0.doc
..........................................\.......\VHDL\readme.txt
..........................................\.......\....\Serial\Source\clock_management.vhd
..........................................\.......\....\......\......\PROM_reader_serial.vhd
..........................................\.......\....\......\......\shift_compare_serial.vhd
..........................................\.......\....\......\.imulation\clock_management.vhd
..........................................\.......\....\......\..........\PROM_reader_serial.vhd
..........................................\.......\....\......\..........\prom_stim_serial.vhd
..........................................\.......\....\......\..........\shift_compare_serial.vhd
..........................................\.......\....\......\..........\sim.do
..........................................\.......\....\......\..........\stimulus_serial.txt
..........................................\.......\....\......\..........\testbench_serial.vhd
..........................................\.......\....\Parallel\Source\clock_management.vhd
..........................................\.......\....\........\......\PROM_reader_parallel.vhd
..........................................\.......\....\........\......\shift_compare_parallel.vhd
..........................................\.......\....\........\.imulation\clock_management.vhd
..........................................\.......\....\........\..........\PROM_reader_parallel.vhd
..........................................\.......\....\........\..........\prom_stim_parallel.vhd
..........................................\.......\....\........\..........\shift_compare_parallel.vhd
..........................................\.......\....\........\..........\sim.do
..........................................\.......\....\........\..........\stimulus_parallel.txt
..........................................\.......\....\........\..........\testbench_parallel.vhd
..........................................\.......\.erilog\readme.txt
..........................................\.......\.......\Serial\Source\clock_management.v
..........................................\.......\.......\......\......\my_LUT2.v
..........................................\.......\.......\......\......\PROM_reader_serial.v
..........................................\.......\.......\......\......\shift_compare_serial.v
..........................................\.......\.......\......\.imulation\clock_management.v
..........................................\.......\.......\......\..........\glbl.v
..........................................\.......\.......\......\..........\my_LUT2.v
..........................................\.......\.......\......\..........\PROM_reader_serial.v
..........................................\.......\.......\......\..........\prom_stim_serial.vhd
..........................................\.......\.......\......\..........\shift_compare_serial.v
..........................................\.......\.......\......\..........\sim.do
..........................................\.......\.......\......\..........\stimulus_serial.txt
..........................................\.......\.......\......\..........\testfixture_serial.v
..........................................\.......\.......\Parallel\Source\clock_management.v
..........................................\.......\.......\........\......\my_LUT2.v
..........................................\.......\.......\........\......\PROM_reader_parallel.v
..........................................\.......\.......\........\......\shift_compare_parallel.v
..........................................\.......\.......\........\.imulation\clock_management.v
..........................................\.......\.......\........\..........\glbl.v
..........................