文件名称:uart
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verilog uart串口通讯程序设计 带个模块详细设计 及说明文档-Verilog the uart serial communication program design with the detailed design and documentation of a module
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下载文件列表
读我.txt
UART设计文档.pdf
fpga\V0p10\uart.qpf
....\.....\uart.qsf
....\.....\uart_description.txt
....\.....\uart.map.smsg
....\.....\uart.map.summary
....\.....\uart.pin
....\.....\uart.fit.smsg
....\.....\uart.fit.summary
....\.....\uart.sof
....\.....\uart.pof
....\.....\uart.tan.summary
....\.....\uart.done
....\.....\uart.dpf
....\.....\uart.cdf
....\.....\top.bsf
....\.....\src\txd.v
....\.....\...\uart.v
....\.....\...\divider.v
....\.....\...\ebi.v
....\.....\...\rxd.v
....\.....\...\top.v
....\.....\testbench\vsim_stacktrace.vstf
....\.....\.........\transcript
....\.....\.........\vish_stacktrace.vstf
....\.....\.........\top_tb.v
....\.....\.........\ModelSim.jpg
....\.....\.........\tcl_stacktrace.txt
....\.....\.........\vsim.wlf
....\.....\.........\uart.mpf
....\.....\.........\uart.cr.mti
....\.....\.........\cycloneII_v\_info
....\.....\.........\work\_info
....\.....\.........\....\uart\_primary.vhd
....\.....\.........\....\....\_primary.dat
....\.....\.........\....\....\verilog.asm
....\.....\.........\....\rxd\_primary.vhd
....\.....\.........\....\...\_primary.dat
....\.....\.........\....\...\verilog.asm
....\.....\.........\....\txd\_primary.vhd
....\.....\.........\....\...\_primary.dat
....\.....\.........\....\...\verilog.asm
....\.....\.........\....\.op\_primary.vhd
....\.....\.........\....\...\_primary.dat
....\.....\.........\....\...\verilog.asm
....\.....\.........\....\ebi\_primary.vhd
....\.....\.........\....\...\_primary.dat
....\.....\.........\....\...\verilog.asm
....\.....\.........\....\division\_primary.vhd
....\.....\.........\....\........\_primary.dat
....\.....\.........\....\........\verilog.asm
....\.....\.........\....\....der\_primary.vhd
....\.....\.........\....\.......\_primary.dat
....\.....\.........\....\.......\verilog.asm
....\.....\.........\....\top_tb\_primary.vhd
....\.....\.........\....\......\_primary.dat
....\.....\.........\....\......\verilog.asm
....\.....\uart.map.rpt
....\.....\uart.fit.rpt
....\.....\uart.asm.rpt
....\.....\uart.tan.rpt
....\.....\uart.flow.rpt
....\.....\uart.qws
Mcu\UartTest\stdinc.h
...\........\UartCtrl.c
...\........\UartTest.eww
...\........\UartTest.ewp
...\........\UartTest.ewd
...\........\UartTest.dep
...\........\main.c
...\........\FpgaInc.h
...\........\UartCtrl.h
...\........\settings\test.cspy.bat
...\........\........\test.dni
...\........\........\test.wsdt
...\........\........\test.dbgdt
...\........\........\UartTest.cspy.bat
...\........\........\UartTest.wsdt
...\........\........\UartTest.dni
fpga\V0p10\testbench\work\uart
....\.....\.........\....\rxd
....\.....\.........\....\txd
....\.....\.........\....\top
....\.....\.........\....\ebi
....\.....\.........\....\division
....\.....\.........\....\divider
....\.....\.........\....\top_tb
....\.....\.........\....\_temp
....\.....\.........\cycloneII_v
....\.....\.........\work
Mcu\UartTest\Debug\Exe
...\........\.....\Obj
...\........\.....\List
fpga\V0p10\src
....\.....\testbench
....\.....\db
Mcu\UartTest\settings
...\........\Debug
fpga\V0p10
UART设计文档.pdf
fpga\V0p10\uart.qpf
....\.....\uart.qsf
....\.....\uart_description.txt
....\.....\uart.map.smsg
....\.....\uart.map.summary
....\.....\uart.pin
....\.....\uart.fit.smsg
....\.....\uart.fit.summary
....\.....\uart.sof
....\.....\uart.pof
....\.....\uart.tan.summary
....\.....\uart.done
....\.....\uart.dpf
....\.....\uart.cdf
....\.....\top.bsf
....\.....\src\txd.v
....\.....\...\uart.v
....\.....\...\divider.v
....\.....\...\ebi.v
....\.....\...\rxd.v
....\.....\...\top.v
....\.....\testbench\vsim_stacktrace.vstf
....\.....\.........\transcript
....\.....\.........\vish_stacktrace.vstf
....\.....\.........\top_tb.v
....\.....\.........\ModelSim.jpg
....\.....\.........\tcl_stacktrace.txt
....\.....\.........\vsim.wlf
....\.....\.........\uart.mpf
....\.....\.........\uart.cr.mti
....\.....\.........\cycloneII_v\_info
....\.....\.........\work\_info
....\.....\.........\....\uart\_primary.vhd
....\.....\.........\....\....\_primary.dat
....\.....\.........\....\....\verilog.asm
....\.....\.........\....\rxd\_primary.vhd
....\.....\.........\....\...\_primary.dat
....\.....\.........\....\...\verilog.asm
....\.....\.........\....\txd\_primary.vhd
....\.....\.........\....\...\_primary.dat
....\.....\.........\....\...\verilog.asm
....\.....\.........\....\.op\_primary.vhd
....\.....\.........\....\...\_primary.dat
....\.....\.........\....\...\verilog.asm
....\.....\.........\....\ebi\_primary.vhd
....\.....\.........\....\...\_primary.dat
....\.....\.........\....\...\verilog.asm
....\.....\.........\....\division\_primary.vhd
....\.....\.........\....\........\_primary.dat
....\.....\.........\....\........\verilog.asm
....\.....\.........\....\....der\_primary.vhd
....\.....\.........\....\.......\_primary.dat
....\.....\.........\....\.......\verilog.asm
....\.....\.........\....\top_tb\_primary.vhd
....\.....\.........\....\......\_primary.dat
....\.....\.........\....\......\verilog.asm
....\.....\uart.map.rpt
....\.....\uart.fit.rpt
....\.....\uart.asm.rpt
....\.....\uart.tan.rpt
....\.....\uart.flow.rpt
....\.....\uart.qws
Mcu\UartTest\stdinc.h
...\........\UartCtrl.c
...\........\UartTest.eww
...\........\UartTest.ewp
...\........\UartTest.ewd
...\........\UartTest.dep
...\........\main.c
...\........\FpgaInc.h
...\........\UartCtrl.h
...\........\settings\test.cspy.bat
...\........\........\test.dni
...\........\........\test.wsdt
...\........\........\test.dbgdt
...\........\........\UartTest.cspy.bat
...\........\........\UartTest.wsdt
...\........\........\UartTest.dni
fpga\V0p10\testbench\work\uart
....\.....\.........\....\rxd
....\.....\.........\....\txd
....\.....\.........\....\top
....\.....\.........\....\ebi
....\.....\.........\....\division
....\.....\.........\....\divider
....\.....\.........\....\top_tb
....\.....\.........\....\_temp
....\.....\.........\cycloneII_v
....\.....\.........\work
Mcu\UartTest\Debug\Exe
...\........\.....\Obj
...\........\.....\List
fpga\V0p10\src
....\.....\testbench
....\.....\db
Mcu\UartTest\settings
...\........\Debug
fpga\V0p10