文件名称:UART-and-FPGA
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基于FPGA的UART通信控制器
设计与实现持。用到modelsim6.1f环境模拟。-UART communication controller based on FPGA
Design and Implementation of hold. Used modelsim6.1f environment simulation.
设计与实现持。用到modelsim6.1f环境模拟。-UART communication controller based on FPGA
Design and Implementation of hold. Used modelsim6.1f environment simulation.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
毕业设计VDHL代码
................\gh_DECODE_3to8.vhd
................\gh_baud_rate_gen.vhd
................\gh_binary2gray.vhd
................\gh_counter_down_ce_ld.vhd
................\gh_counter_down_ce_ld_tc.vhd
................\gh_counter_integer_down.vhd
................\gh_edge_det.vhd
................\gh_edge_det_XCD.vhd
................\gh_fifo_async16_rcsr_wf.vhd
................\gh_fifo_async16_sr.vhd
................\gh_gray2binary.vhd
................\gh_jkff.vhd
................\gh_parity_gen_Serial.vhd
................\gh_register_ce.vhd
................\gh_shift_reg_PL_sl.vhd
................\gh_shift_reg_se_sl.vhd
................\gh_uart_16550.vhd
................\gh_uart_Rx_8bit.vhd
................\gh_uart_Tx_8bit.vhd
................\uart_to_uart.vhd
................\gh_DECODE_3to8.vhd
................\gh_baud_rate_gen.vhd
................\gh_binary2gray.vhd
................\gh_counter_down_ce_ld.vhd
................\gh_counter_down_ce_ld_tc.vhd
................\gh_counter_integer_down.vhd
................\gh_edge_det.vhd
................\gh_edge_det_XCD.vhd
................\gh_fifo_async16_rcsr_wf.vhd
................\gh_fifo_async16_sr.vhd
................\gh_gray2binary.vhd
................\gh_jkff.vhd
................\gh_parity_gen_Serial.vhd
................\gh_register_ce.vhd
................\gh_shift_reg_PL_sl.vhd
................\gh_shift_reg_se_sl.vhd
................\gh_uart_16550.vhd
................\gh_uart_Rx_8bit.vhd
................\gh_uart_Tx_8bit.vhd
................\uart_to_uart.vhd