文件名称:s22_DCT

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 400kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • lip***
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

这是一个DCT变换的VERILOG代码,欢迎下载-This is a code of DCT transformation in verilog ,welcome to download!
(系统自动生成,下载前可以参看下载内容)

下载文件列表

s22_DCT\dct\1ddct\.untf

.......\...\.....\1ddct.dhp

.......\...\.....\1ddct.ise

.......\...\.....\1ddct.ise_ISE_Backup

.......\...\.....\automake.log

.......\...\.....\d1_dct.v

.......\...\.....\dct.bld

.......\...\.....\dct.cmd_log

.......\...\.....\dct.lso

.......\...\.....\dct.mrp

.......\...\.....\dct.nc1

.......\...\.....\dct.ncd

.......\...\.....\dct.ngc

.......\...\.....\dct.ngd

.......\...\.....\dct.ngm

.......\...\.....\dct.ngr

.......\...\.....\dct.pad

.......\...\.....\dct.pad_txt

.......\...\.....\dct.par

.......\...\.....\dct.par_nlf

.......\...\.....\dct.pcf

.......\...\.....\dct.placed_ncd_tracker

.......\...\.....\dct.prj

.......\...\.....\dct.routed_ncd_tracker

.......\...\.....\dct.stx

.......\...\.....\dct.syr

.......\...\.....\dct.twr

.......\...\.....\dct.twx

.......\...\.....\dct.versim_par

.......\...\.....\dct.xpi

.......\...\.....\dct_map.ncd

.......\...\.....\dct_map.ngm

.......\...\.....\dct_pad.csv

.......\...\.....\dct_pad.txt

.......\...\.....\dct_summary.html

.......\...\.....\dct_test.cmd_log

.......\...\.....\dct_test.lso

.......\...\.....\dct_test.prj

.......\...\.....\dct_test.syr

.......\...\.....\dct_test_summary.html

.......\...\.....\dct_test_vhdl.prj

.......\...\.....\dct_timesim.nlf

.......\...\.....\dct_timesim.sdf

.......\...\.....\dct_timesim.v

.......\...\.....\dct_vhdl.prj

.......\...\.....\idtest.ant

.......\...\.....\idtest.fdo

.......\...\.....\idtest.jhd

.......\...\.....\idtest.tbw

.......\...\.....\idtest.tdo

.......\...\.....\idtest.tfw

.......\...\.....\idtest.timesim_tfw

.......\...\.....\idtest.udo

.......\...\.....\idtest.xwv

.......\...\.....\idtest.xwv_bak

.......\...\.....\idtest_bencher.prj

.......\...\.....\Project.dhp

.......\...\.....\results.txt

.......\...\.....\transcript

.......\...\.....\vsim.wlf

.......\...\.....\work\dct\verilog.asm

.......\...\.....\....\...\_primary.dat

.......\...\.....\....\...\_primary.vhd

.......\...\.....\....\glbl\verilog.asm

.......\...\.....\....\....\_primary.dat

.......\...\.....\....\....\_primary.vhd

.......\...\.....\....\idtest\verilog.asm

.......\...\.....\....\......\_primary.dat

.......\...\.....\....\......\_primary.vhd

.......\...\.....\....\_info

.......\...\.....\xst\work\hdllib.ref

.......\...\.....\...\....\vlg27\dct.bin

.......\...\.....\...\....\...36\dct__test.bin

.......\...\.....\_ngo\netlist.lst

.......\...\.....\._projnav\1ddct.gfl

.......\...\.....\.........\1ddct_flowplus.gfl

.......\...\.....\.........\dct.xst

.......\...\.....\.........\dct_test.xst

.......\...\.....\.........\ednTOngd_tcl.rsp

.......\...\.....\.........\nc1TOncd_tcl.rsp

.......\...\.....\.........\netgen_par_tcl.rsp

.......\...\.....\.........\runXst_tcl.rsp

.......\...\.....\.........\sumrpt_tcl.rsp

.......\...\.....\__projnav.log

.......\...\introduce.txt

.......\...\rtl\d1_dct.v

.......\...\...\d2_dct.v

.......\...\1ddct\xst\dump.xst\dct.prj\ngx\notopt

.......\...\.....\...\........\.......\...\opt

.......\...\.....\...\........\..._test.prj\ngx\notopt

.......\...\.....\...\........\............\...\opt

.......\...\.....\...\........\....prj\ngx

.......\...\.....\...\........\..._test.prj\ngx

.......\...\.....\...\........\dct.prj

.......\...\.....\...\........\dct_test.prj

.......\...\.....\...\work\vlg27

.......\...\.....\...\....\vlg36

.......\...\.....\work\dct

.......\...\.....\....\glbl

.......\...\.....\....\idtest

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