文件名称:mulitcpu
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用verilog HDL语言或者VHDL语言来编写，实现多时钟周期CPU的设计。能够完成以下二十二条指定（均不考虑虚拟地址和Cache，并且默认为小端方式）：
add rd, rs, rt
addu rd, rs, rt
addi rt, rs, imm
addiu rt, rs, imm
sub rd, rs, rt
subu rd, rs, rt
nor rd, rs, rt
xori rt, rs, imm
clo
clz
slt rd, rs, rt
sltu rd, rs, rt
slti rt, rs, imm
sltiu rt, rs, imm
sllv rd, rt, rs
sra rd, rt, shamt
blez rs, imm
j target
lwl rt, offset(base)
lwr rt, offset(base)
lw rt, imm(rs)
sw rt, imm(rs)
-Verilog HDL language or VHDL language to write multi-clock cycle of the CPU design. To complete the following 22 specified (not taking into account the virtual address and the Cache and the default Xiaoduan):
add rd, rs, rt
addu rd, rs, rt
addi rt, rs, imm
addiu rt, rs, imm
sub rd, rs, rt
subu rd, rs, rt
of nor rd, rs, rt
xori rt, rs, imm
clo
clz
slt rd, rs, rt
sltu rd, rs, rt
slti rt, rs, imm
sltiu rt, rs, imm
sllv rd, rt, rs
sra rd, rt, shamt
blez rs, imm
j target
lwl rt, offset (base)
lwr rt, offset (base)
lw rt, imm (rs)
sw rt, imm (rs)Undo edits
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add rd, rs, rt
addu rd, rs, rt
addi rt, rs, imm
addiu rt, rs, imm
sub rd, rs, rt
subu rd, rs, rt
nor rd, rs, rt
xori rt, rs, imm
clo
clz
slt rd, rs, rt
sltu rd, rs, rt
slti rt, rs, imm
sltiu rt, rs, imm
sllv rd, rt, rs
sra rd, rt, shamt
blez rs, imm
j target
lwl rt, offset(base)
lwr rt, offset(base)
lw rt, imm(rs)
sw rt, imm(rs)
-Verilog HDL language or VHDL language to write multi-clock cycle of the CPU design. To complete the following 22 specified (not taking into account the virtual address and the Cache and the default Xiaoduan):
add rd, rs, rt
addu rd, rs, rt
addi rt, rs, imm
addiu rt, rs, imm
sub rd, rs, rt
subu rd, rs, rt
of nor rd, rs, rt
xori rt, rs, imm
clo
clz
slt rd, rs, rt
sltu rd, rs, rt
slti rt, rs, imm
sltiu rt, rs, imm
sllv rd, rt, rs
sra rd, rt, shamt
blez rs, imm
j target
lwl rt, offset (base)
lwr rt, offset (base)
lw rt, imm (rs)
sw rt, imm (rs)Undo edits
DictionaryGoogle Translate for Business:Translator ToolkitWebsite TranslatorGlobal Market Finder
(系统自动生成,下载前可以参看下载内容)
下载文件列表
mulitcpu\visio\多周期CPU数据通路.vsd
........\.....\指令执行状态转换图.vsd
........\代码\ALU.v
........\....\CPU_control.v
........\....\extender.v
........\....\I_type_control.v
........\....\memory.v
........\....\multi_cpu.v
........\....\registers.v
........\....\register_single.v
........\....\R_type_control.v
........\....\selector1.v
........\....\selector32.v
........\....\selector32_3.v
........\....\selector32_4.v
........\....\selector4_3.v
........\....\selector5.v
........\....\shift.v
........\multiCPU\ALU.v
........\........\CPU_control.v
........\........\CPU_control.v.bak
........\........\db\multi_cpu.atom.rvd
........\........\..\multi_cpu.cbx.xml
........\........\..\multi_cpu.cmp.rdb
........\........\..\multi_cpu.cmp_merge.kpt
........\........\..\multi_cpu.db_info
........\........\..\multi_cpu.eco.cdb
........\........\..\multi_cpu.eds_overflow
........\........\..\multi_cpu.fnsim.cdb
........\........\..\multi_cpu.fnsim.hdb
........\........\..\multi_cpu.fnsim.qmsg
........\........\..\multi_cpu.hier_info
........\........\..\multi_cpu.hif
........\........\..\multi_cpu.lpc.html
........\........\..\multi_cpu.lpc.rdb
........\........\..\multi_cpu.lpc.txt
........\........\..\multi_cpu.map.bpm
........\........\..\multi_cpu.map.cdb
........\........\..\multi_cpu.map.ecobp
........\........\..\multi_cpu.map.hdb
........\........\..\multi_cpu.map.kpt
........\........\..\multi_cpu.map.logdb
........\........\..\multi_cpu.map.qmsg
........\........\..\multi_cpu.map_bb.cdb
........\........\..\multi_cpu.map_bb.hdb
........\........\..\multi_cpu.map_bb.logdb
........\........\..\multi_cpu.pre_map.cdb
........\........\..\multi_cpu.pre_map.hdb
........\........\..\multi_cpu.rpp.qmsg
........\........\..\multi_cpu.rtlv.hdb
........\........\..\multi_cpu.rtlv_sg.cdb
........\........\..\multi_cpu.rtlv_sg_swap.cdb
........\........\..\multi_cpu.sgate.rvd
........\........\..\multi_cpu.sgate_sm.rvd
........\........\..\multi_cpu.sgdiff.cdb
........\........\..\multi_cpu.sgdiff.hdb
........\........\..\multi_cpu.sim.cvwf
........\........\..\multi_cpu.sim.hdb
........\........\..\multi_cpu.sim.qmsg
........\........\..\multi_cpu.sim.rdb
........\........\..\multi_cpu.simfam
........\........\..\multi_cpu.sld_design_entry.sci
........\........\..\multi_cpu.sld_design_entry_dsc.sci
........\........\..\multi_cpu.smp_dump.txt
........\........\..\multi_cpu.syn_hier_info
........\........\..\multi_cpu.tis_db_list.ddb
........\........\..\multi_cpu.tmw_info
........\........\..\mux_3nc.tdf
........\........\..\mux_aqc.tdf
........\........\..\mux_ioc.tdf
........\........\..\mux_joc.tdf
........\........\..\prev_cmp_multi_cpu.map.qmsg
........\........\..\prev_cmp_multi_cpu.qmsg
........\........\..\prev_cmp_multi_cpu.sim.qmsg
........\........\..\wed.wsf
........\........\.ebug\multi_cpu.done
........\........\.....\multi_cpu.flow.rpt
........\........\.....\multi_cpu.map.rpt
........\........\.....\multi_cpu.map.smsg
........\........\.....\multi_cpu.map.summary
........\........\.....\multi_cpu.sim.rpt
........\........\extender.v
........\........\incremental_db\compiled_partitions\multi_cpu.root_partition.map.atm
........\........\..............\...................\multi_cpu.root_partition.map.dpi
........\........\..............\...................\multi_cpu.root_partition.map.hdbx
........\........\..............\...................\multi_cpu.root_partition.map.kpt
........\........\..............\README
........\........\I_type_control.v
........\........\I_type_control.v.bak
........\........\memory.v
........\........\memory.v.bak
........\........\multi_cpu.qpf
........\........\multi_cpu.qsf
........\........\multi_cpu.qws
........\........\multi_cpu.v
........\........\multi_cpu.v.bak
........\........\multi_cpu.vwf
........\........\registers.v
........\........\registers.v.bak
........\........\register_single.v
........\.....\指令执行状态转换图.vsd
........\代码\ALU.v
........\....\CPU_control.v
........\....\extender.v
........\....\I_type_control.v
........\....\memory.v
........\....\multi_cpu.v
........\....\registers.v
........\....\register_single.v
........\....\R_type_control.v
........\....\selector1.v
........\....\selector32.v
........\....\selector32_3.v
........\....\selector32_4.v
........\....\selector4_3.v
........\....\selector5.v
........\....\shift.v
........\multiCPU\ALU.v
........\........\CPU_control.v
........\........\CPU_control.v.bak
........\........\db\multi_cpu.atom.rvd
........\........\..\multi_cpu.cbx.xml
........\........\..\multi_cpu.cmp.rdb
........\........\..\multi_cpu.cmp_merge.kpt
........\........\..\multi_cpu.db_info
........\........\..\multi_cpu.eco.cdb
........\........\..\multi_cpu.eds_overflow
........\........\..\multi_cpu.fnsim.cdb
........\........\..\multi_cpu.fnsim.hdb
........\........\..\multi_cpu.fnsim.qmsg
........\........\..\multi_cpu.hier_info
........\........\..\multi_cpu.hif
........\........\..\multi_cpu.lpc.html
........\........\..\multi_cpu.lpc.rdb
........\........\..\multi_cpu.lpc.txt
........\........\..\multi_cpu.map.bpm
........\........\..\multi_cpu.map.cdb
........\........\..\multi_cpu.map.ecobp
........\........\..\multi_cpu.map.hdb
........\........\..\multi_cpu.map.kpt
........\........\..\multi_cpu.map.logdb
........\........\..\multi_cpu.map.qmsg
........\........\..\multi_cpu.map_bb.cdb
........\........\..\multi_cpu.map_bb.hdb
........\........\..\multi_cpu.map_bb.logdb
........\........\..\multi_cpu.pre_map.cdb
........\........\..\multi_cpu.pre_map.hdb
........\........\..\multi_cpu.rpp.qmsg
........\........\..\multi_cpu.rtlv.hdb
........\........\..\multi_cpu.rtlv_sg.cdb
........\........\..\multi_cpu.rtlv_sg_swap.cdb
........\........\..\multi_cpu.sgate.rvd
........\........\..\multi_cpu.sgate_sm.rvd
........\........\..\multi_cpu.sgdiff.cdb
........\........\..\multi_cpu.sgdiff.hdb
........\........\..\multi_cpu.sim.cvwf
........\........\..\multi_cpu.sim.hdb
........\........\..\multi_cpu.sim.qmsg
........\........\..\multi_cpu.sim.rdb
........\........\..\multi_cpu.simfam
........\........\..\multi_cpu.sld_design_entry.sci
........\........\..\multi_cpu.sld_design_entry_dsc.sci
........\........\..\multi_cpu.smp_dump.txt
........\........\..\multi_cpu.syn_hier_info
........\........\..\multi_cpu.tis_db_list.ddb
........\........\..\multi_cpu.tmw_info
........\........\..\mux_3nc.tdf
........\........\..\mux_aqc.tdf
........\........\..\mux_ioc.tdf
........\........\..\mux_joc.tdf
........\........\..\prev_cmp_multi_cpu.map.qmsg
........\........\..\prev_cmp_multi_cpu.qmsg
........\........\..\prev_cmp_multi_cpu.sim.qmsg
........\........\..\wed.wsf
........\........\.ebug\multi_cpu.done
........\........\.....\multi_cpu.flow.rpt
........\........\.....\multi_cpu.map.rpt
........\........\.....\multi_cpu.map.smsg
........\........\.....\multi_cpu.map.summary
........\........\.....\multi_cpu.sim.rpt
........\........\extender.v
........\........\incremental_db\compiled_partitions\multi_cpu.root_partition.map.atm
........\........\..............\...................\multi_cpu.root_partition.map.dpi
........\........\..............\...................\multi_cpu.root_partition.map.hdbx
........\........\..............\...................\multi_cpu.root_partition.map.kpt
........\........\..............\README
........\........\I_type_control.v
........\........\I_type_control.v.bak
........\........\memory.v
........\........\memory.v.bak
........\........\multi_cpu.qpf
........\........\multi_cpu.qsf
........\........\multi_cpu.qws
........\........\multi_cpu.v
........\........\multi_cpu.v.bak
........\........\multi_cpu.vwf
........\........\registers.v
........\........\registers.v.bak
........\........\register_single.v