文件名称:sy4
介绍说明－－下载内容均来自于网络，请自行研究使用
D74LS74
JK74ls112.
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
ENTITY D74LS74 is
port(clk,clr,PRE,D:in std_logic
QT,QTN:out std_logic)
end ENTITY D74LS74
architecture bhv of D74LS74 is
signal q,qn:std_logic
signal x:std_logic
begin
x<=d -LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
ENTITY D74LS74 is
port(clk,clr,PRE,D:in std_logic
QT,QTN:out std_logic)
end ENTITY D74LS74
architecture bhv of D74LS74 is
signal q,qn:std_logic
signal x:std_logic
begin
x<=d
JK74ls112.
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
ENTITY D74LS74 is
port(clk,clr,PRE,D:in std_logic
QT,QTN:out std_logic)
end ENTITY D74LS74
architecture bhv of D74LS74 is
signal q,qn:std_logic
signal x:std_logic
begin
x<=d -LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
ENTITY D74LS74 is
port(clk,clr,PRE,D:in std_logic
QT,QTN:out std_logic)
end ENTITY D74LS74
architecture bhv of D74LS74 is
signal q,qn:std_logic
signal x:std_logic
begin
x<=d
(系统自动生成,下载前可以参看下载内容)
下载文件列表
D74LS74.txt
JK74ls112..txt
JK74ls112..txt