shizi39\a12.vhd.bak

.......\a12_1.vhd

.......\a12_1.vhd.bak

.......\a24.vhd

.......\a24.vhd.bak

.......\a60.vhd

.......\a60.vhd.bak

.......\a60.vwf

.......\a601.vhd

.......\a601.vhd.bak

.......\chengx\clock_vhdl.asm.rpt

.......\......\clock_vhdl.bdf

.......\......\clock_vhdl.done

.......\......\clock_vhdl.fit.rpt

.......\......\clock_vhdl.fit.summary

.......\......\clock_vhdl.flow.rpt

.......\......\clock_vhdl.map.rpt

.......\......\clock_vhdl.map.summary

.......\......\clock_vhdl.pin

.......\......\clock_vhdl.pof

.......\......\clock_vhdl.qpf

.......\......\clock_vhdl.qsf

.......\......\clock_vhdl.qws

.......\......\clock_vhdl.sim.rpt

.......\......\clock_vhdl.sof

.......\......\clock_vhdl.tan.rpt

.......\......\clock_vhdl.tan.summary

.......\......\clock_vhdl.vwf

.......\......\count24.bsf

.......\......\count24.vhd

.......\......\count60.bsf

.......\......\count60.vhd

.......\......\db\add_sub_0ih.tdf

.......\......\..\add_sub_jlh.tdf

.......\......\..\add_sub_klh.tdf

.......\......\..\clock_vhdl.asm.qmsg

.......\......\..\clock_vhdl.cbx.xml

.......\......\..\clock_vhdl.cmp.cdb

.......\......\..\clock_vhdl.cmp.hdb

.......\......\..\clock_vhdl.cmp.logdb

.......\......\..\clock_vhdl.cmp.rdb

.......\......\..\clock_vhdl.cmp.tdb

.......\......\..\clock_vhdl.cmp0.ddb

.......\......\..\clock_vhdl.db_info

.......\......\..\clock_vhdl.eco.cdb

.......\......\..\clock_vhdl.eds_overflow

.......\......\..\clock_vhdl.fit.qmsg

.......\......\..\clock_vhdl.fnsim.hdb

.......\......\..\clock_vhdl.fnsim.qmsg

.......\......\..\clock_vhdl.hier_info

.......\......\..\clock_vhdl.hif

.......\......\..\clock_vhdl.map.cdb

.......\......\..\clock_vhdl.map.hdb

.......\......\..\clock_vhdl.map.logdb

.......\......\..\clock_vhdl.map.qmsg

.......\......\..\clock_vhdl.pre_map.cdb

.......\......\..\clock_vhdl.pre_map.hdb

.......\......\..\clock_vhdl.rtlv.hdb

.......\......\..\clock_vhdl.rtlv_sg.cdb

.......\......\..\clock_vhdl.rtlv_sg_swap.cdb

.......\......\..\clock_vhdl.sgdiff.cdb

.......\......\..\clock_vhdl.sgdiff.hdb

.......\......\..\clock_vhdl.sim.cvwf

.......\......\..\clock_vhdl.sim.hdb

.......\......\..\clock_vhdl.sim.qmsg

.......\......\..\clock_vhdl.sim.rdb

.......\......\..\clock_vhdl.sld_design_entry.sci

.......\......\..\clock_vhdl.sld_design_entry_dsc.sci

.......\......\..\clock_vhdl.syn_hier_info

.......\......\..\clock_vhdl.tan.qmsg

.......\......\..\clock_vhdl.tis_db_list.ddb

.......\......\..\clock_vhdl.tmw_info

.......\......\..\mux_1ac.tdf

.......\......\..\mux_hbc.tdf

.......\......\..\prev_cmp_clock_vhdl.asm.qmsg

.......\......\..\prev_cmp_clock_vhdl.fit.qmsg

.......\......\..\prev_cmp_clock_vhdl.map.qmsg

.......\......\..\prev_cmp_clock_vhdl.qmsg

.......\......\..\prev_cmp_clock_vhdl.tan.qmsg

.......\......\..\wed.wsf

.......\......\display.bsf

.......\......\display.vhd

.......\......\incremental_db\compiled_partitions\clock_vhdl.root_partition.map.kpt

.......\......\..............\README

.......\......\mux_21.bsf

.......\......\mux_21.vhd

.......\......\mux_21.vhd.bak

.......\clock.asm.rpt

.......\clock.bdf

.......\clock.done

.......\clock.fit.rpt

.......\clock.fit.smsg

.......\clock.fit.summary

.......\clock.flow.rpt

.......\clock.map.rpt

.......\clock.map.summary

.......\clock.pin

.......\clock.pof

.......\clock.qpf

.......\clock.qsf