文件名称:MEMCTRL
介绍说明－－下载内容均来自于网络，请自行研究使用
基于verilog的存储控制器芯片设计的工程。使用 Quartus II 4.0 以上版本打开设计工程文件。-Based on the works of the the verilog storage controller chip design. Use the Quartus II 4.0 or later to open the design engineering documents.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
MEMCTRL\CMP_STATE.INI
.......\DB\ADD_SUB_D5H.TDF
.......\..\ADD_SUB_E5H.TDF
.......\..\ADD_SUB_FCH.TDF
.......\..\ADD_SUB_JHH.TDF
.......\..\ADD_SUB_N6H.TDF
.......\..\MC_TOP-SIM.VWF
.......\..\MC_TOP.ASM.QMSG
.......\..\MC_TOP.CMP.CDB
.......\..\MC_TOP.CMP.DDB
.......\..\MC_TOP.CMP.HDB
.......\..\MC_TOP.CMP.RDB
.......\..\MC_TOP.CMP.TDB
.......\..\MC_TOP.CSF.QMSG
.......\..\MC_TOP.DB_INFO
.......\..\MC_TOP.EDA.QMSG
.......\..\MC_TOP.FIT.QMSG
.......\..\MC_TOP.HIF
.......\..\MC_TOP.ICC
.......\..\MC_TOP.MAP.CDB
.......\..\MC_TOP.MAP.HDB
.......\..\MC_TOP.MAP.QMSG
.......\..\MC_TOP.MC_TOP.SLD_DESIGN_ENTRY.SCI
.......\..\MC_TOP.PRE_MAP.HDB
.......\..\MC_TOP.PROJECT.HDB
.......\..\MC_TOP.RTLV.HDB
.......\..\MC_TOP.RTLV_SG.CDB
.......\..\MC_TOP.RTLV_SG_SWAP.CDB
.......\..\MC_TOP.SGDIFF.CDB
.......\..\MC_TOP.SGDIFF.HDB
.......\..\MC_TOP.SIGNALPROBE.CDB
.......\..\MC_TOP.SIM.HDB
.......\..\MC_TOP.SIM.QMSG
.......\..\MC_TOP.SIM.RDB
.......\..\MC_TOP.TAN.QMSG
.......\..\MC_TOP_CMP.QRPT
.......\..\MC_TOP_HIER_INFO
.......\..\MC_TOP_SIM.QRPT
.......\..\MC_TOP_SYN_HIER_INFO
.......\MC_ADR_SEL.V
.......\MC_CS_RF.V
.......\MC_DEFINES.V
.......\MC_DEFINES.V.BAK
.......\MC_DP.V
.......\MC_INCN_R.V
.......\MC_MEM_IF.V
.......\MC_OBCT.V
.......\MC_OBCT_TOP.V
.......\MC_RD_FIFO.V
.......\MC_REFRESH.V
.......\MC_RF.V
.......\MC_TIMING.V
.......\MC_TOP.ASM.RPT
.......\MC_TOP.DONE
.......\MC_TOP.EDA.RPT
.......\MC_TOP.FIT.EQN
.......\MC_TOP.FIT.RPT
.......\MC_TOP.FLOW.RPT
.......\MC_TOP.MAP.EQN
.......\MC_TOP.MAP.RPT
.......\MC_TOP.PIN
.......\MC_TOP.POF
.......\MC_TOP.QPF
.......\MC_TOP.QSF
.......\MC_TOP.QWS
.......\MC_TOP.SIM.RPT
.......\MC_TOP.SOF
.......\MC_TOP.TAN.RPT
.......\MC_TOP.TAN.SUMMARY
.......\MC_TOP.V
.......\MC_TOP.VWF
.......\MC_WB_IF.V
.......\SIMULATION\MODELSIM\MC_TOP.VO
.......\..........\........\MC_TOP_MODELSIM.XRF
.......\..........\........\MC_TOP_V.SDO
.......\VERILOG\160B3VER\ADV_BB.V
.......\.......\........\CVS\ENTRIES
.......\.......\........\...\REPOSITORY
.......\.......\........\...\ROOT
.......\.......\........\DP160B3B.V
.......\.......\........\DP160B3B_RU.V
.......\.......\........\DP160B3T.V
.......\.......\........\F160B3B.BKB
.......\.......\........\F160B3B.BKE
.......\.......\........\F160B3B.BKT
.......\.......\........\F160B3T.BKB
.......\.......\........\F160B3T.BKE
.......\.......\........\F160B3T.BKT
.......\.......\........\READ.ME
.......\.......\........\T160B3B.V
.......\.......\........\T160B3T.V
.......\.......\CVS\ENTRIES
.......\.......\...\REPOSITORY
.......\.......\...\ROOT
.......\.......\SDRAM_MODELS\16MX16\CVS\ENTRIES
.......\.......\............\......\...\REPOSITORY
.......\.......\............\......\...\ROOT
.......\.......\............\......\MT48LC16M16A2.V
.......\.......\............\....8\CVS\ENTRIES
.......\.......\............\.....\...\REPOSITORY
.......\DB\ADD_SUB_D5H.TDF
.......\..\ADD_SUB_E5H.TDF
.......\..\ADD_SUB_FCH.TDF
.......\..\ADD_SUB_JHH.TDF
.......\..\ADD_SUB_N6H.TDF
.......\..\MC_TOP-SIM.VWF
.......\..\MC_TOP.ASM.QMSG
.......\..\MC_TOP.CMP.CDB
.......\..\MC_TOP.CMP.DDB
.......\..\MC_TOP.CMP.HDB
.......\..\MC_TOP.CMP.RDB
.......\..\MC_TOP.CMP.TDB
.......\..\MC_TOP.CSF.QMSG
.......\..\MC_TOP.DB_INFO
.......\..\MC_TOP.EDA.QMSG
.......\..\MC_TOP.FIT.QMSG
.......\..\MC_TOP.HIF
.......\..\MC_TOP.ICC
.......\..\MC_TOP.MAP.CDB
.......\..\MC_TOP.MAP.HDB
.......\..\MC_TOP.MAP.QMSG
.......\..\MC_TOP.MC_TOP.SLD_DESIGN_ENTRY.SCI
.......\..\MC_TOP.PRE_MAP.HDB
.......\..\MC_TOP.PROJECT.HDB
.......\..\MC_TOP.RTLV.HDB
.......\..\MC_TOP.RTLV_SG.CDB
.......\..\MC_TOP.RTLV_SG_SWAP.CDB
.......\..\MC_TOP.SGDIFF.CDB
.......\..\MC_TOP.SGDIFF.HDB
.......\..\MC_TOP.SIGNALPROBE.CDB
.......\..\MC_TOP.SIM.HDB
.......\..\MC_TOP.SIM.QMSG
.......\..\MC_TOP.SIM.RDB
.......\..\MC_TOP.TAN.QMSG
.......\..\MC_TOP_CMP.QRPT
.......\..\MC_TOP_HIER_INFO
.......\..\MC_TOP_SIM.QRPT
.......\..\MC_TOP_SYN_HIER_INFO
.......\MC_ADR_SEL.V
.......\MC_CS_RF.V
.......\MC_DEFINES.V
.......\MC_DEFINES.V.BAK
.......\MC_DP.V
.......\MC_INCN_R.V
.......\MC_MEM_IF.V
.......\MC_OBCT.V
.......\MC_OBCT_TOP.V
.......\MC_RD_FIFO.V
.......\MC_REFRESH.V
.......\MC_RF.V
.......\MC_TIMING.V
.......\MC_TOP.ASM.RPT
.......\MC_TOP.DONE
.......\MC_TOP.EDA.RPT
.......\MC_TOP.FIT.EQN
.......\MC_TOP.FIT.RPT
.......\MC_TOP.FLOW.RPT
.......\MC_TOP.MAP.EQN
.......\MC_TOP.MAP.RPT
.......\MC_TOP.PIN
.......\MC_TOP.POF
.......\MC_TOP.QPF
.......\MC_TOP.QSF
.......\MC_TOP.QWS
.......\MC_TOP.SIM.RPT
.......\MC_TOP.SOF
.......\MC_TOP.TAN.RPT
.......\MC_TOP.TAN.SUMMARY
.......\MC_TOP.V
.......\MC_TOP.VWF
.......\MC_WB_IF.V
.......\SIMULATION\MODELSIM\MC_TOP.VO
.......\..........\........\MC_TOP_MODELSIM.XRF
.......\..........\........\MC_TOP_V.SDO
.......\VERILOG\160B3VER\ADV_BB.V
.......\.......\........\CVS\ENTRIES
.......\.......\........\...\REPOSITORY
.......\.......\........\...\ROOT
.......\.......\........\DP160B3B.V
.......\.......\........\DP160B3B_RU.V
.......\.......\........\DP160B3T.V
.......\.......\........\F160B3B.BKB
.......\.......\........\F160B3B.BKE
.......\.......\........\F160B3B.BKT
.......\.......\........\F160B3T.BKB
.......\.......\........\F160B3T.BKE
.......\.......\........\F160B3T.BKT
.......\.......\........\READ.ME
.......\.......\........\T160B3B.V
.......\.......\........\T160B3T.V
.......\.......\CVS\ENTRIES
.......\.......\...\REPOSITORY
.......\.......\...\ROOT
.......\.......\SDRAM_MODELS\16MX16\CVS\ENTRIES
.......\.......\............\......\...\REPOSITORY
.......\.......\............\......\...\ROOT
.......\.......\............\......\MT48LC16M16A2.V
.......\.......\............\....8\CVS\ENTRIES
.......\.......\............\.....\...\REPOSITORY