文件名称:pipeline_cpu
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流水线cpu，pipeline_cpu,南大计算机系计算机组成原理实验-Pipeline cpu, pipeline_cpu, Nanjing University Department of Computer Science Computer Composition principle experiment
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下载文件列表
pipeline_cpu\visio图\Branch指令.vsd
............\.......\Exec.vsd
............\.......\IUnit.vsd
............\.......\I型指令.vsd
............\.......\Load-use检测前.vsd
............\.......\Load-use检测后.vsd
............\.......\Load_use.vsd
............\.......\load指令.vsd
............\.......\PipelineCPU总数据通路.vsd
............\.......\R型指令.vsd
............\.......\store指令.vsd
............\.......\加入loaduse冒险控制后的数据通路.vsd
............\.......\单周期数据通路.vsd
............\.......\寄存器的读写时机.vsd
............\.......\带转发和阻塞的数据通路图.vsd
............\.......\带转发的数据通路.vsd
............\.......\带转发的流水线控制.vsd
............\.......\控制信号.vsd
............\.......\控制冒险.vsd
............\.......\数据冒险.vsd
............\.......\数据冒险（解决）.vsd
............\.......\流水线数据通路.vsd
............\.......\流水线数据通路amy.vsd
............\.......\流水线流程示意.vsd
............\.......\流水线流程示意2.vsd
............\.......\结构冒险.vsd
............\.......\结构冒险（解决）.vsd
............\.......\转发条件和路径.vsd
............\文档\各模块信号表.doc
............\....\指令序列.docx
............\流水线\ADDER.v
............\......\ADDER.v.bak
............\......\alu.v
............\......\alu.v.bak
............\......\Branch_unit.v
............\......\Control_unit.v
............\......\Control_unit.v.bak
............\......\db\add_sub_8ri.tdf
............\......\..\mux_3nc.tdf
............\......\..\mux_aqc.tdf
............\......\..\mux_ioc.tdf
............\......\..\mux_k6d.tdf
............\......\..\mux_umc.tdf
............\......\..\pipeline_cpu.asm.qmsg
............\......\..\pipeline_cpu.cbx.xml
............\......\..\pipeline_cpu.cmp.ecobp
............\......\..\pipeline_cpu.cmp.kpt
............\......\..\pipeline_cpu.cmp.rdb
............\......\..\pipeline_cpu.cmp0.ddb
............\......\..\pipeline_cpu.cmp_merge.kpt
............\......\..\pipeline_cpu.db_info
............\......\..\pipeline_cpu.eco.cdb
............\......\..\pipeline_cpu.eds_overflow
............\......\..\pipeline_cpu.fit.qmsg
............\......\..\pipeline_cpu.fnsim.cdb
............\......\..\pipeline_cpu.fnsim.hdb
............\......\..\pipeline_cpu.fnsim.qmsg
............\......\..\pipeline_cpu.hier_info
............\......\..\pipeline_cpu.hif
............\......\..\pipeline_cpu.lpc.html
............\......\..\pipeline_cpu.lpc.rdb
............\......\..\pipeline_cpu.lpc.txt
............\......\..\pipeline_cpu.map.bpm
............\......\..\pipeline_cpu.map.cdb
............\......\..\pipeline_cpu.map.ecobp
............\......\..\pipeline_cpu.map.hdb
............\......\..\pipeline_cpu.map.kpt
............\......\..\pipeline_cpu.map.logdb
............\......\..\pipeline_cpu.map.qmsg
............\......\..\pipeline_cpu.map_bb.cdb
............\......\..\pipeline_cpu.map_bb.hdb
............\......\..\pipeline_cpu.map_bb.logdb
............\......\..\pipeline_cpu.pre_map.cdb
............\......\..\pipeline_cpu.pre_map.hdb
............\......\..\pipeline_cpu.rpp.qmsg
............\......\..\pipeline_cpu.rtlv.hdb
............\......\..\pipeline_cpu.rtlv_sg.cdb
............\......\..\pipeline_cpu.rtlv_sg_swap.cdb
............\......\..\pipeline_cpu.sgate.rvd
............\......\..\pipeline_cpu.sgate_sm.rvd
............\......\..\pipeline_cpu.sgdiff.cdb
............\......\..\pipeline_cpu.sgdiff.hdb
............\......\..\pipeline_cpu.sim.cvwf
............\......\..\pipeline_cpu.sim.hdb
............\......\..\pipeline_cpu.sim.qmsg
............\......\..\pipeline_cpu.sim.rdb
............\......\..\pipeline_cpu.simfam
............\......\..\pipeline_cpu.sld_design_entry.sci
............\......\..\pipeline_cpu.sld_design_entry_dsc.sci
............\......\..\pipeline_cpu.syn_hier_info
............\......\..\pipeline_cpu.tan.qmsg
............\......\..\pipeline_cpu.tis_db_list.ddb
............\......\..\pipeline_cpu.tmw_info
............\......\..\pipeline_cpu_global_asgn_op.abo
............\......\..\prev_cmp_pipeline_cpu.asm.qmsg
............\......\..\prev_cmp_pipeline_cpu.fit.qmsg
............\..
............\.......\Exec.vsd
............\.......\IUnit.vsd
............\.......\I型指令.vsd
............\.......\Load-use检测前.vsd
............\.......\Load-use检测后.vsd
............\.......\Load_use.vsd
............\.......\load指令.vsd
............\.......\PipelineCPU总数据通路.vsd
............\.......\R型指令.vsd
............\.......\store指令.vsd
............\.......\加入loaduse冒险控制后的数据通路.vsd
............\.......\单周期数据通路.vsd
............\.......\寄存器的读写时机.vsd
............\.......\带转发和阻塞的数据通路图.vsd
............\.......\带转发的数据通路.vsd
............\.......\带转发的流水线控制.vsd
............\.......\控制信号.vsd
............\.......\控制冒险.vsd
............\.......\数据冒险.vsd
............\.......\数据冒险（解决）.vsd
............\.......\流水线数据通路.vsd
............\.......\流水线数据通路amy.vsd
............\.......\流水线流程示意.vsd
............\.......\流水线流程示意2.vsd
............\.......\结构冒险.vsd
............\.......\结构冒险（解决）.vsd
............\.......\转发条件和路径.vsd
............\文档\各模块信号表.doc
............\....\指令序列.docx
............\流水线\ADDER.v
............\......\ADDER.v.bak
............\......\alu.v
............\......\alu.v.bak
............\......\Branch_unit.v
............\......\Control_unit.v
............\......\Control_unit.v.bak
............\......\db\add_sub_8ri.tdf
............\......\..\mux_3nc.tdf
............\......\..\mux_aqc.tdf
............\......\..\mux_ioc.tdf
............\......\..\mux_k6d.tdf
............\......\..\mux_umc.tdf
............\......\..\pipeline_cpu.asm.qmsg
............\......\..\pipeline_cpu.cbx.xml
............\......\..\pipeline_cpu.cmp.ecobp
............\......\..\pipeline_cpu.cmp.kpt
............\......\..\pipeline_cpu.cmp.rdb
............\......\..\pipeline_cpu.cmp0.ddb
............\......\..\pipeline_cpu.cmp_merge.kpt
............\......\..\pipeline_cpu.db_info
............\......\..\pipeline_cpu.eco.cdb
............\......\..\pipeline_cpu.eds_overflow
............\......\..\pipeline_cpu.fit.qmsg
............\......\..\pipeline_cpu.fnsim.cdb
............\......\..\pipeline_cpu.fnsim.hdb
............\......\..\pipeline_cpu.fnsim.qmsg
............\......\..\pipeline_cpu.hier_info
............\......\..\pipeline_cpu.hif
............\......\..\pipeline_cpu.lpc.html
............\......\..\pipeline_cpu.lpc.rdb
............\......\..\pipeline_cpu.lpc.txt
............\......\..\pipeline_cpu.map.bpm
............\......\..\pipeline_cpu.map.cdb
............\......\..\pipeline_cpu.map.ecobp
............\......\..\pipeline_cpu.map.hdb
............\......\..\pipeline_cpu.map.kpt
............\......\..\pipeline_cpu.map.logdb
............\......\..\pipeline_cpu.map.qmsg
............\......\..\pipeline_cpu.map_bb.cdb
............\......\..\pipeline_cpu.map_bb.hdb
............\......\..\pipeline_cpu.map_bb.logdb
............\......\..\pipeline_cpu.pre_map.cdb
............\......\..\pipeline_cpu.pre_map.hdb
............\......\..\pipeline_cpu.rpp.qmsg
............\......\..\pipeline_cpu.rtlv.hdb
............\......\..\pipeline_cpu.rtlv_sg.cdb
............\......\..\pipeline_cpu.rtlv_sg_swap.cdb
............\......\..\pipeline_cpu.sgate.rvd
............\......\..\pipeline_cpu.sgate_sm.rvd
............\......\..\pipeline_cpu.sgdiff.cdb
............\......\..\pipeline_cpu.sgdiff.hdb
............\......\..\pipeline_cpu.sim.cvwf
............\......\..\pipeline_cpu.sim.hdb
............\......\..\pipeline_cpu.sim.qmsg
............\......\..\pipeline_cpu.sim.rdb
............\......\..\pipeline_cpu.simfam
............\......\..\pipeline_cpu.sld_design_entry.sci
............\......\..\pipeline_cpu.sld_design_entry_dsc.sci
............\......\..\pipeline_cpu.syn_hier_info
............\......\..\pipeline_cpu.tan.qmsg
............\......\..\pipeline_cpu.tis_db_list.ddb
............\......\..\pipeline_cpu.tmw_info
............\......\..\pipeline_cpu_global_asgn_op.abo
............\......\..\prev_cmp_pipeline_cpu.asm.qmsg
............\......\..\prev_cmp_pipeline_cpu.fit.qmsg
............\..