文件名称:All-DigitalQPSK-Demodulator
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II 8．1开发环境下，完成了中频全数字解调器的FPGA实现，并对数
字下变频、载波同步、位同步等解调器的核心模块设计进行了详细的分析和说明，给出
了实现框图和仿真波形。同时在本设计中应用了Altera公司的NiosII软核处理器技术，
用于载波的大频偏校正和解调器各个部分的监测和控制。最后给出了QPSK中频全数字
解调器关键性能指标的测试方法和测试结果，测试结果表明本设计达到了预期的性能指
标要求。-The Algorithm is converted to HDL descr iption for FPGA realization．The designs of the core Modules of demodulator, including digital down-conversion，carrier ring，bit synchronization loop design, are described in detail．And a block diagram and simulated waveforms are provide in the latter part．Also the soft-core processor technology of Altera’s NiosII is applied in the design for carrier frequency offset correction and the monitoring and control of the separate parts of demodulator．Finally, the test methods and results of key performance indicators of the IF Demodulator QPSK are given to show that the design given in this paper can reach the performance requirements expected.
II 8．1开发环境下，完成了中频全数字解调器的FPGA实现，并对数
字下变频、载波同步、位同步等解调器的核心模块设计进行了详细的分析和说明，给出
了实现框图和仿真波形。同时在本设计中应用了Altera公司的NiosII软核处理器技术，
用于载波的大频偏校正和解调器各个部分的监测和控制。最后给出了QPSK中频全数字
解调器关键性能指标的测试方法和测试结果，测试结果表明本设计达到了预期的性能指
标要求。-The Algorithm is converted to HDL descr iption for FPGA realization．The designs of the core Modules of demodulator, including digital down-conversion，carrier ring，bit synchronization loop design, are described in detail．And a block diagram and simulated waveforms are provide in the latter part．Also the soft-core processor technology of Altera’s NiosII is applied in the design for carrier frequency offset correction and the monitoring and control of the separate parts of demodulator．Finally, the test methods and results of key performance indicators of the IF Demodulator QPSK are given to show that the design given in this paper can reach the performance requirements expected.
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QPSK中频全数字解调器的设计与FPGA实现.pdf