文件名称:1HZ
介绍说明－－下载内容均来自于网络，请自行研究使用
1hz 分频器设计，基于dsp的程序，在实验板上调试通过，运行正确-1hz frequency
(系统自动生成,下载前可以参看下载内容)
下载文件列表
1HZ\BZ_CLK.asm.rpt
...\BZ_CLK.cdf
...\BZ_CLK.done
...\BZ_CLK.dpf
...\BZ_CLK.fit.rpt
...\BZ_CLK.fit.smsg
...\BZ_CLK.fit.summary
...\BZ_CLK.flow.rpt
...\BZ_CLK.map.rpt
...\BZ_CLK.map.summary
...\BZ_CLK.pin
...\BZ_CLK.pof
...\BZ_CLK.qpf
...\BZ_CLK.qsf
...\BZ_CLK.qws
...\BZ_CLK.sof
...\BZ_CLK.tan.rpt
...\BZ_CLK.tan.summary
...\BZ_CLK.vhd
...\BZ_CLK.vhd.bak
...\BZ_CLK_description.txt
...\CLK_DV8.bsf
...\CLK_DV8.vhd
...\db\BZ_CLK.asm.qmsg
...\..\BZ_CLK.asm_labs.ddb
...\..\BZ_CLK.cbx.xml
...\..\BZ_CLK.cmp.bpm
...\..\BZ_CLK.cmp.cdb
...\..\BZ_CLK.cmp.ecobp
...\..\BZ_CLK.cmp.hdb
...\..\BZ_CLK.cmp.logdb
...\..\BZ_CLK.cmp.rdb
...\..\BZ_CLK.cmp.tdb
...\..\BZ_CLK.cmp0.ddb
...\..\BZ_CLK.cmp2.ddb
...\..\BZ_CLK.cmp_bb.cdb
...\..\BZ_CLK.cmp_bb.hdb
...\..\BZ_CLK.cmp_bb.logdb
...\..\BZ_CLK.cmp_bb.rcf
...\..\BZ_CLK.dbp
...\..\BZ_CLK.db_info
...\..\BZ_CLK.eco.cdb
...\..\BZ_CLK.fit.qmsg
...\..\BZ_CLK.hier_info
...\..\BZ_CLK.hif
...\..\BZ_CLK.map.bpm
...\..\BZ_CLK.map.cdb
...\..\BZ_CLK.map.ecobp
...\..\BZ_CLK.map.hdb
...\..\BZ_CLK.map.logdb
...\..\BZ_CLK.map.qmsg
...\..\BZ_CLK.map_bb.cdb
...\..\BZ_CLK.map_bb.hdb
...\..\BZ_CLK.map_bb.logdb
...\..\BZ_CLK.pre_map.cdb
...\..\BZ_CLK.pre_map.hdb
...\..\BZ_CLK.psp
...\..\BZ_CLK.pss
...\..\BZ_CLK.rpp.qmsg
...\..\BZ_CLK.rtlv.hdb
...\..\BZ_CLK.rtlv_sg.cdb
...\..\BZ_CLK.rtlv_sg_swap.cdb
...\..\BZ_CLK.sgate.rvd
...\..\BZ_CLK.sgate_sm.rvd
...\..\BZ_CLK.sgdiff.cdb
...\..\BZ_CLK.sgdiff.hdb
...\..\BZ_CLK.signalprobe.cdb
...\..\BZ_CLK.sld_design_entry.sci
...\..\BZ_CLK.sld_design_entry_dsc.sci
...\..\BZ_CLK.syn_hier_info
...\..\BZ_CLK.tan.qmsg
...\..\BZ_CLK.tis_db_list.ddb
...\..\prev_cmp_BZ_CLK.asm.qmsg
...\..\prev_cmp_BZ_CLK.fit.qmsg
...\..\prev_cmp_BZ_CLK.map.qmsg
...\..\prev_cmp_BZ_CLK.qmsg
...\..\prev_cmp_BZ_CLK.tan.qmsg
...\db
1HZ
...\BZ_CLK.cdf
...\BZ_CLK.done
...\BZ_CLK.dpf
...\BZ_CLK.fit.rpt
...\BZ_CLK.fit.smsg
...\BZ_CLK.fit.summary
...\BZ_CLK.flow.rpt
...\BZ_CLK.map.rpt
...\BZ_CLK.map.summary
...\BZ_CLK.pin
...\BZ_CLK.pof
...\BZ_CLK.qpf
...\BZ_CLK.qsf
...\BZ_CLK.qws
...\BZ_CLK.sof
...\BZ_CLK.tan.rpt
...\BZ_CLK.tan.summary
...\BZ_CLK.vhd
...\BZ_CLK.vhd.bak
...\BZ_CLK_description.txt
...\CLK_DV8.bsf
...\CLK_DV8.vhd
...\db\BZ_CLK.asm.qmsg
...\..\BZ_CLK.asm_labs.ddb
...\..\BZ_CLK.cbx.xml
...\..\BZ_CLK.cmp.bpm
...\..\BZ_CLK.cmp.cdb
...\..\BZ_CLK.cmp.ecobp
...\..\BZ_CLK.cmp.hdb
...\..\BZ_CLK.cmp.logdb
...\..\BZ_CLK.cmp.rdb
...\..\BZ_CLK.cmp.tdb
...\..\BZ_CLK.cmp0.ddb
...\..\BZ_CLK.cmp2.ddb
...\..\BZ_CLK.cmp_bb.cdb
...\..\BZ_CLK.cmp_bb.hdb
...\..\BZ_CLK.cmp_bb.logdb
...\..\BZ_CLK.cmp_bb.rcf
...\..\BZ_CLK.dbp
...\..\BZ_CLK.db_info
...\..\BZ_CLK.eco.cdb
...\..\BZ_CLK.fit.qmsg
...\..\BZ_CLK.hier_info
...\..\BZ_CLK.hif
...\..\BZ_CLK.map.bpm
...\..\BZ_CLK.map.cdb
...\..\BZ_CLK.map.ecobp
...\..\BZ_CLK.map.hdb
...\..\BZ_CLK.map.logdb
...\..\BZ_CLK.map.qmsg
...\..\BZ_CLK.map_bb.cdb
...\..\BZ_CLK.map_bb.hdb
...\..\BZ_CLK.map_bb.logdb
...\..\BZ_CLK.pre_map.cdb
...\..\BZ_CLK.pre_map.hdb
...\..\BZ_CLK.psp
...\..\BZ_CLK.pss
...\..\BZ_CLK.rpp.qmsg
...\..\BZ_CLK.rtlv.hdb
...\..\BZ_CLK.rtlv_sg.cdb
...\..\BZ_CLK.rtlv_sg_swap.cdb
...\..\BZ_CLK.sgate.rvd
...\..\BZ_CLK.sgate_sm.rvd
...\..\BZ_CLK.sgdiff.cdb
...\..\BZ_CLK.sgdiff.hdb
...\..\BZ_CLK.signalprobe.cdb
...\..\BZ_CLK.sld_design_entry.sci
...\..\BZ_CLK.sld_design_entry_dsc.sci
...\..\BZ_CLK.syn_hier_info
...\..\BZ_CLK.tan.qmsg
...\..\BZ_CLK.tis_db_list.ddb
...\..\prev_cmp_BZ_CLK.asm.qmsg
...\..\prev_cmp_BZ_CLK.fit.qmsg
...\..\prev_cmp_BZ_CLK.map.qmsg
...\..\prev_cmp_BZ_CLK.qmsg
...\..\prev_cmp_BZ_CLK.tan.qmsg
...\db
1HZ