文件名称:e_32_16
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8位串行数据转32位数据在转换为两个16位数据的verilog HDL代码。-8-bit serial data transfer 32-bit data into two 16-bit data verilog HDL code.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
e_32_16
.......\e_32_16.v
.......\e_32_16.v.bak
.......\tb
.......\..\e_32_16_test.v
.......\..\e_32_16_test.v.bak
.......\..\run.bat
.......\..\sim.do
.......\..\sim.do.bak
.......\..\transcript
.......\..\vsim.wlf
.......\..\wlft6e39q3
.......\..\work
.......\..\....\e_32
.......\..\....\....\verilog.asm
.......\..\....\....\verilog.rw
.......\..\....\....\_primary.dat
.......\..\....\....\_primary.dbs
.......\..\....\....\_primary.vhd
.......\..\....\e_32_16
.......\..\....\.......\verilog.asm
.......\..\....\.......\verilog.rw
.......\..\....\.......\_primary.dat
.......\..\....\.......\_primary.dbs
.......\..\....\.......\_primary.vhd
.......\..\....\e_32_16_test
.......\..\....\............\verilog.asm
.......\..\....\............\verilog.rw
.......\..\....\............\_primary.dat
.......\..\....\............\_primary.dbs
.......\..\....\............\_primary.vhd
.......\..\....\e_32_test
.......\..\....\.........\verilog.asm
.......\..\....\.........\verilog.rw
.......\..\....\.........\_primary.dat
.......\..\....\.........\_primary.dbs
.......\..\....\.........\_primary.vhd
.......\..\....\_info
.......\..\....\_temp
.......\..\....\.....\vlog7b1621
.......\..\....\.....\vlog7dq5h8
.......\..\....\.....\vlogavtcdt
.......\..\....\.....\vlogb4bzi9
.......\..\....\.....\vlogc7qdjt
.......\..\....\.....\vlogci34bv
.......\..\....\.....\vlogdw8ewv
.......\..\....\.....\vloge9kkvq
.......\..\....\.....\vloggn9myq
.......\..\....\.....\vlogvva2s8
.......\..\....\.....\vlogx14v4y
.......\..\....\.....\vlogxh3vkj
.......\..\....\_vmake
.......\e_32_16.v
.......\e_32_16.v.bak
.......\tb
.......\..\e_32_16_test.v
.......\..\e_32_16_test.v.bak
.......\..\run.bat
.......\..\sim.do
.......\..\sim.do.bak
.......\..\transcript
.......\..\vsim.wlf
.......\..\wlft6e39q3
.......\..\work
.......\..\....\e_32
.......\..\....\....\verilog.asm
.......\..\....\....\verilog.rw
.......\..\....\....\_primary.dat
.......\..\....\....\_primary.dbs
.......\..\....\....\_primary.vhd
.......\..\....\e_32_16
.......\..\....\.......\verilog.asm
.......\..\....\.......\verilog.rw
.......\..\....\.......\_primary.dat
.......\..\....\.......\_primary.dbs
.......\..\....\.......\_primary.vhd
.......\..\....\e_32_16_test
.......\..\....\............\verilog.asm
.......\..\....\............\verilog.rw
.......\..\....\............\_primary.dat
.......\..\....\............\_primary.dbs
.......\..\....\............\_primary.vhd
.......\..\....\e_32_test
.......\..\....\.........\verilog.asm
.......\..\....\.........\verilog.rw
.......\..\....\.........\_primary.dat
.......\..\....\.........\_primary.dbs
.......\..\....\.........\_primary.vhd
.......\..\....\_info
.......\..\....\_temp
.......\..\....\.....\vlog7b1621
.......\..\....\.....\vlog7dq5h8
.......\..\....\.....\vlogavtcdt
.......\..\....\.....\vlogb4bzi9
.......\..\....\.....\vlogc7qdjt
.......\..\....\.....\vlogci34bv
.......\..\....\.....\vlogdw8ewv
.......\..\....\.....\vloge9kkvq
.......\..\....\.....\vloggn9myq
.......\..\....\.....\vlogvva2s8
.......\..\....\.....\vlogx14v4y
.......\..\....\.....\vlogxh3vkj
.......\..\....\_vmake