文件名称:user_design
介绍说明－－下载内容均来自于网络，请自行研究使用
spartan3a-ddr2 (16bits 333M)
(系统自动生成,下载前可以参看下载内容)
下载文件列表
user_design\datasheet.txt
...........\log.txt
...........\mig.prj
...........\par\create_ise.bat
...........\...\icon_coregen.xco
...........\...\ila_coregen.xco
...........\...\ise_flow.bat
...........\...\ise_run.txt
...........\...\makeproj.bat
...........\...\mem_interface_top.ut
...........\...\readme.txt
...........\...\rem_files.bat
...........\...\set_ise_prop.tcl
...........\...\spartan3A_DDR2_test_mig_v3_6.cdc
...........\...\spartan3A_DDR2_test_mig_v3_6.ucf
...........\...\vio_coregen.xco
...........\rtl\spartan3A_DDR2_test_mig_v3_6.v
...........\...\spartan3A_DDR2_test_mig_v3_6_cal_ctl.v
...........\...\spartan3A_DDR2_test_mig_v3_6_cal_top.v
...........\...\spartan3A_DDR2_test_mig_v3_6_clk_dcm.v
...........\...\spartan3A_DDR2_test_mig_v3_6_controller_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_controller_iobs_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_data_path_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_data_path_iobs_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_data_read_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_data_read_controller_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_data_write_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_dqs_delay.v
...........\...\spartan3A_DDR2_test_mig_v3_6_fifo_0_wr_en_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_fifo_1_wr_en_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_infrastructure.v
...........\...\spartan3A_DDR2_test_mig_v3_6_infrastructure_iobs_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_infrastructure_top.v
...........\...\spartan3A_DDR2_test_mig_v3_6_iobs_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_parameters_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_ram8d_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_rd_gray_cntr.v
...........\...\spartan3A_DDR2_test_mig_v3_6_s3_dm_iob.v
...........\...\spartan3A_DDR2_test_mig_v3_6_s3_dqs_iob.v
...........\...\spartan3A_DDR2_test_mig_v3_6_s3_dq_iob.v
...........\...\spartan3A_DDR2_test_mig_v3_6_tap_dly.v
...........\...\spartan3A_DDR2_test_mig_v3_6_top_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_wr_gray_cntr.v
...........\sim\ddr2_model.v
...........\...\ddr2_model_parameters.vh
...........\...\sim.do
...........\...\sim_tb_top.v
...........\...\spartan3A_DDR2_test_mig_v3_6_addr_gen_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_cmd_fsm_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_cmp_data_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_data_gen_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_test_bench_0.v
...........\...\transcript
...........\...\vsim.wlf
...........\...\wiredly.v
...........\...\.ork\@wire@delay\verilog.asm
...........\...\....\...........\verilog.psm
...........\...\....\...........\verilog.rw
...........\...\....\...........\_primary.dat
...........\...\....\...........\_primary.dbs
...........\...\....\...........\_primary.vhd
...........\...\....\ddr2_model\verilog.asm
...........\...\....\..........\verilog.psm
...........\...\....\..........\verilog.rw
...........\...\....\..........\_primary.dat
...........\...\....\..........\_primary.dbs
...........\...\....\..........\_primary.vhd
...........\...\....\glbl\verilog.asm
...........\...\....\....\verilog.psm
...........\...\....\....\verilog.rw
...........\...\....\....\_primary.dat
...........\...\....\....\_primary.dbs
...........\...\....\....\_primary.vhd
...........\...\....\icon\verilog.asm
...........\...\....\....\verilog.psm
...........\...\....\....\verilog.rw
...........\...\....\....\_primary.dat
...........\...\....\....\_primary.dbs
...........\...\....\....\_primary.vhd
...........\...\....\.la\verilog.asm
...........\...\....\...\verilog.psm
...........\...\....\...\verilog.rw
...........\...\....\...\_primary.dat
...........\...\....\...\_primary.dbs
...........\...\....\...\_primary.vhd
...........\...\....\sim_tb_top\verilog.asm
...........\...\....\..........\verilog.psm
...........\...\....\..........\verilog.rw
...........\...\....\..........\_primary.dat
...........\...\....\..........\_primary.dbs
...........\...\....\..........\_primary.vhd
...........\...\
...........\log.txt
...........\mig.prj
...........\par\create_ise.bat
...........\...\icon_coregen.xco
...........\...\ila_coregen.xco
...........\...\ise_flow.bat
...........\...\ise_run.txt
...........\...\makeproj.bat
...........\...\mem_interface_top.ut
...........\...\readme.txt
...........\...\rem_files.bat
...........\...\set_ise_prop.tcl
...........\...\spartan3A_DDR2_test_mig_v3_6.cdc
...........\...\spartan3A_DDR2_test_mig_v3_6.ucf
...........\...\vio_coregen.xco
...........\rtl\spartan3A_DDR2_test_mig_v3_6.v
...........\...\spartan3A_DDR2_test_mig_v3_6_cal_ctl.v
...........\...\spartan3A_DDR2_test_mig_v3_6_cal_top.v
...........\...\spartan3A_DDR2_test_mig_v3_6_clk_dcm.v
...........\...\spartan3A_DDR2_test_mig_v3_6_controller_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_controller_iobs_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_data_path_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_data_path_iobs_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_data_read_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_data_read_controller_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_data_write_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_dqs_delay.v
...........\...\spartan3A_DDR2_test_mig_v3_6_fifo_0_wr_en_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_fifo_1_wr_en_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_infrastructure.v
...........\...\spartan3A_DDR2_test_mig_v3_6_infrastructure_iobs_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_infrastructure_top.v
...........\...\spartan3A_DDR2_test_mig_v3_6_iobs_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_parameters_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_ram8d_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_rd_gray_cntr.v
...........\...\spartan3A_DDR2_test_mig_v3_6_s3_dm_iob.v
...........\...\spartan3A_DDR2_test_mig_v3_6_s3_dqs_iob.v
...........\...\spartan3A_DDR2_test_mig_v3_6_s3_dq_iob.v
...........\...\spartan3A_DDR2_test_mig_v3_6_tap_dly.v
...........\...\spartan3A_DDR2_test_mig_v3_6_top_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_wr_gray_cntr.v
...........\sim\ddr2_model.v
...........\...\ddr2_model_parameters.vh
...........\...\sim.do
...........\...\sim_tb_top.v
...........\...\spartan3A_DDR2_test_mig_v3_6_addr_gen_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_cmd_fsm_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_cmp_data_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_data_gen_0.v
...........\...\spartan3A_DDR2_test_mig_v3_6_test_bench_0.v
...........\...\transcript
...........\...\vsim.wlf
...........\...\wiredly.v
...........\...\.ork\@wire@delay\verilog.asm
...........\...\....\...........\verilog.psm
...........\...\....\...........\verilog.rw
...........\...\....\...........\_primary.dat
...........\...\....\...........\_primary.dbs
...........\...\....\...........\_primary.vhd
...........\...\....\ddr2_model\verilog.asm
...........\...\....\..........\verilog.psm
...........\...\....\..........\verilog.rw
...........\...\....\..........\_primary.dat
...........\...\....\..........\_primary.dbs
...........\...\....\..........\_primary.vhd
...........\...\....\glbl\verilog.asm
...........\...\....\....\verilog.psm
...........\...\....\....\verilog.rw
...........\...\....\....\_primary.dat
...........\...\....\....\_primary.dbs
...........\...\....\....\_primary.vhd
...........\...\....\icon\verilog.asm
...........\...\....\....\verilog.psm
...........\...\....\....\verilog.rw
...........\...\....\....\_primary.dat
...........\...\....\....\_primary.dbs
...........\...\....\....\_primary.vhd
...........\...\....\.la\verilog.asm
...........\...\....\...\verilog.psm
...........\...\....\...\verilog.rw
...........\...\....\...\_primary.dat
...........\...\....\...\_primary.dbs
...........\...\....\...\_primary.vhd
...........\...\....\sim_tb_top\verilog.asm
...........\...\....\..........\verilog.psm
...........\...\....\..........\verilog.rw
...........\...\....\..........\_primary.dat
...........\...\....\..........\_primary.dbs
...........\...\....\..........\_primary.vhd
...........\...\