文件名称:Simulink-to-VHDL-Route
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This paper presents the way of speeding up the route
from the oretical design with Simulink/Matlab, via
behavioral simulation in fixed-point arithmetic to the
implementation on either FPGA or custom silicon. This has
been achieved by porting the netlist of the Simulink system
descr iption into the VHDL. At the first instance, the
Simulink-to-VHDL converter has been designed to use
structural VHDL code to describe system interconnections,
allowing simple behavioral descr iptions for basic blocks.
The resulting VHDL code delivers bit-true result when
compared to the equivalent fixed-point Simulink model
simulations.-This paper presents the way of speeding up the route
from the theoretical design with Simulink/Matlab, via
behavioral simulation in fixed-point arithmetic to the
implementation on either FPGA or custom silicon. This has
been achieved by porting the netlist of the Simulink system
descr iption into the VHDL. At the first instance, the
Simulink-to-VHDL converter has been designed to use
structural VHDL code to describe system interconnections,
allowing simple behavioral descr iptions for basic blocks.
The resulting VHDL code delivers bit-true result when
compared to the equivalent fixed-point Simulink model
simulations.
from the oretical design with Simulink/Matlab, via
behavioral simulation in fixed-point arithmetic to the
implementation on either FPGA or custom silicon. This has
been achieved by porting the netlist of the Simulink system
descr iption into the VHDL. At the first instance, the
Simulink-to-VHDL converter has been designed to use
structural VHDL code to describe system interconnections,
allowing simple behavioral descr iptions for basic blocks.
The resulting VHDL code delivers bit-true result when
compared to the equivalent fixed-point Simulink model
simulations.-This paper presents the way of speeding up the route
from the theoretical design with Simulink/Matlab, via
behavioral simulation in fixed-point arithmetic to the
implementation on either FPGA or custom silicon. This has
been achieved by porting the netlist of the Simulink system
descr iption into the VHDL. At the first instance, the
Simulink-to-VHDL converter has been designed to use
structural VHDL code to describe system interconnections,
allowing simple behavioral descr iptions for basic blocks.
The resulting VHDL code delivers bit-true result when
compared to the equivalent fixed-point Simulink model
simulations.
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下载文件列表
| 文件名 | 大小 | 更新时间 |
|---|---|---|
| Matlab | Simulink - Simulink Matlab to VHDL Route for Full Custom FPGA Rapid Prototyping of DSP Algorithms.pdf |